Intel Agilex® 7 FPGA F-Series Development Kit User Guide

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ID 683024
Date 1/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kits Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. Software and Driver Installation 2.2. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kit 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Intel® Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab Status Control PMA Setting Data Type Error Control Run Control 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab 4.2.8. Identify Test Pass/Fail based on BTS GUI test status
5. Development Kits Hardware and Configuration x
5.1. Configure the FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in the QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. Intel Agilex® 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. On-board Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kits Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Additional Information

4.2.4. The QSFPDD Tab

The QSFPDD Tab allows you to run transceivers QSFPDDx8 loopback tests on your board. You can run the test using either electrical loopback modules or optical fiber modules.

Figure 9. The QSFPDD Tab

The following sections describe controls in the QSFPDD tab.

Status

The Status control displays the following status information during the loopback test:
  • PLL lock: Shows the PLL locked or unlocked state
  • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence is detected.
  • Detail: Shows the PLL lock and pattern sync status.

Control

Use the following controls to select an interface to apply PMA settings, data type and error control:
  • QSFPDD0 x8
  • QSFPDD1 x8

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
    • Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer.
    • Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.
  • Equalizer: Specifies the RX tuning mode for receiver equalizer.
Figure 10. QSFPDD-PMA Setting

Data Type

The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:
  • PRBS: pseudo-random 7-bit sequences (default)
  • PRBS15: pseudo-random 15-bit sequences
  • PRBS23: pseudo-random 23-bit sequences
  • PRBS31: pseudo-random 31-bit sequences

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the received bit stream.
  • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Bit Error Rate: Calculates the bit error rate of the transmit data stream.
  • Insert: Insert a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.

Run Control

  • TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Start: This control initiates the loopback tests.
  • Data Rate: Displays the XCVR type and data rate of each channel.
Figure 11. XCVR- Data Rate
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