Agilex™ 7 FPGA F-Series Development Kit User Guide

Download PDF
ID 683024
Date 1/16/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Control On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device by AS Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in the QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. Agilex™ 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. On-board Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

5.1. Configure the FPGA and Access HPS Debug Access Port by JTAG

JTAG access does not rely on the SW1 settings and the system MAX® 10 image.

Plug the USB cable to J13 or Intel® FPGA Download Cable to J14.

Open the Quartus® Prime programmer, system console to configure Agilex™ 7 FPGA SDM, system MAX® 10 and PCIe* JTAG nodes.

Open the Arm* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition to connect and communicate with the HPS debug access port (DAP) through the same JTAG interface.

Note: By default, the HPS and FPGA SDM JTAG nodes are chained together internally. SW4 bypasses or enables both nodes at the same time.

If the attestation or Black Key Provisioning (BKP), or both, is enabled on the Agilex™ 7 device, you must use the updated SDM firmware and TCK guidelines (JTAG clock).

  • You must update to the SDM firmware delivered with the Quartus® Prime Pro Edition software version 21.3 and beyond.
  • For the TCK pin, you must either leave the TCK pin unconnected, or connect the TCK pin to the VCCIO_SDM supply using a 10-kΩ pull-up resistor.
Note: The existing guidance in the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series to connect TCK to a 1-k Ω pull-down resistor is included for noise suppression. The change in guidance to a 10-k Ω pull-up resistor is not expected to affect the device functionally.

For more information about connecting the TCK pin, refer to the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series .

Related Information
Level Two Title