Intel Agilex® 7 FPGA F-Series Development Kit User Guide

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ID 683024
Date 1/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kits Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA F-Series Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. Software and Driver Installation 2.2. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kit 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Intel® Quartus® Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kit x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The QSFPDD Tab 4.2.5. The DDR4-0 Tab 4.2.6. The DDR4-2 Tab 4.2.7. The DDR4-3 Tab 4.2.8. Identify Test Pass/Fail based on BTS GUI test status
5. Development Kits Hardware and Configuration x
5.1. Configure the FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in the QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. Intel Agilex® 7 FPGA A.2. Configuration Support A.3. Clocks A.4. Memory Interfaces A.5. Transceiver Interfaces A.6. HPS Interface A.7. General Input and Output A.8. Power
A.2. Configuration Support x
A.2.1. JTAG Chain and Header A.2.2. On-board Intel® FPGA Download Cable II
A.7. General Input and Output x
A.7.1. Switches A.7.2. Buttons A.7.3. LEDs
A.8. Power x
A.8.1. Power Sequence A.8.2. Power Measurement A.8.3. Temperature Monitor
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kits Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA F-Series Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.4. Memory Interfaces

The Intel Agilex® 7 FPGA F-Series Development Kit has four channels of 288 pin DDR4 DIMM 72-bit interfaces: DDR4 DIMM CH0, DDR4 DIMM CH1,DDR4 DIMM CH2 and DDR4 DIMM CH3.

DDR4 DIMM CH1 is designed for HPS dedicated applications. The other three memory channels are for FPGA general usage and support both DDR4 and DDR-T ( Intel® Optane™ PMem modules).

  • DDR4 DIMM CH0 is located in FPGA Bank 3A and 3B. It supports both DDR4 and DDR-T modules.
  • DDR4 DIMM CH1 is located in FPGA Bank 3C and 3D. It only supports DDR4 module.
  • DDR4 DIMM CH2 is located in FPGA Bank 2A and 2B. It supports both DDR4 and DDR-T modules.
  • DDR4 DIMM CH3 is located in FPGA Bank 2C and 2D. It supports both DDR4 and DDR-T modules.
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