Intel Agilex® 7 FPGA F-Series Development Kit User Guide

ID 683024
Date 1/18/2024
Public
Document Table of Contents

3.1. Default Settings

The Intel Agilex® 7 FPGA F-Series Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table given below to return the board to its factory settings before proceeding forward.

Note: X refers to Don't Care in the table below.
Table 4.  Factory Default Switch Settings
Switch Default Position Function
SW1 [1:3] OFF/ON/ON

Configuration mode setting bits

By default, AS -> FAST mode

SW2 [1:4] OFF/OFF/OFF/OFF

Select the resource of the System Intel® MAX® 10 JTAG from USB PHY

Enable Si5341’s outputs

Power up Si52202

Enable UART interface

SW3 [1:4] OFF/OFF/OFF/OFF

Enable all the I2C level shifter.

SW4 [1:4] OFF/ON/ON/OFF

Select on-board Intel® FPGA Download Cable as JTAG master when external JTAG header is absent

Bypass PWR Intel® MAX® 10 in JTAG chain;

Bypass FPGA HPS in JTAG chain

Enable FPGA in JTAG chain

SW5 SW5.5 to SW5.6

Power off the board

SW6 [1:4] ON/OFF/OFF/OFF

PCIe x16 mode is selected

SW7.1 ON

Select local clock as PCIe reference clock