Visible to Intel only — GUID: sfo1410069353681
Ixiasoft
Visible to Intel only — GUID: sfo1410069353681
Ixiasoft
19.3. USB 2.0 ULPI PHY Signal Description
Port Name |
Bit Width |
Direction |
Description |
---|---|---|---|
ulpi_clk |
1 |
Input |
ULPI Clock Receives the 60‑MHz clock supplied by the high‑speed ULPI PHY. All signals are synchronous to the positive edge of the clock. |
ulpi_dir |
1 |
Input |
ULPI Data Bus Control 1—The PHY has data to transfer to the USB OTG controller. 0—The PHY does not have data to transfer. |
ulpi_nxt |
1 |
Input |
ULPI Next Data Control Indicates that the PHY has accepted the current byte from the USB OTG controller. When the PHY is transmitting, this signal indicates that a new byte is available for the controller. |
ulpi_stp |
1 |
Output |
ULPI Stop Data Control The controller drives this signal high to indicate the end of its data stream. The controller can also drive this signal high to request data from the PHY. |
ulpi_data[7:0] | 8 |
Bidirectional |
Bidirectional data bus. Driven low by the controller during idle. |