Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

4.1.2. Reset Controller

The reset controller performs the following functions:

  • Accepts reset requests from the FPGA CB, FPGA fabric, modules in the HPS, and reset pins
  • Generates an individual reset signal for each module instance for all modules in the HPS
  • Provides reset handshaking signals to support system reset behavior

The reset controller generates module reset signals from external reset requests and internal reset requests. External reset requests originate from sources external to the reset manager. Internal reset requests originate from control registers in the reset manager.

The reset controller supports the following cold reset requests:

  • Power-on reset (POR) voltage monitor
  • Cold reset request pin (nPOR)
  • FPGA fabric
  • FPGA CB and scan manager
  • Software cold reset request bit (swcoldrstreq) of the control register (ctrl)

The reset controller supports the following warm reset requests:

  • Warm reset request pin (nRST)
  • FPGA fabric
  • Software warm reset request bit (swwarmrstreq) of the ctrl register
  • MPU watchdog reset requests for CPU0 and CPU1
  • System watchdog timer 0 and 1 reset requests

The reset controller supports the following debug reset requests:

  • CDBGRSTREQ from DAP
  • FPGA fabric
Figure 11. Reset Controller Signals