Visible to Intel only — GUID: cru1429293240877
Ixiasoft
Visible to Intel only — GUID: cru1429293240877
Ixiasoft
8.3.2.3. MPU Address Space
Addresses generated by the MPU are decoded in three ways:
- By default, MPU accesses to locations between 0x100000 (1 MB) to 0xC0000000 (3 GB) are made to the SDRAM controller.
- Addresses in the SCU and L2 register region (0xFFFEC000 to 0xFFFF0000) are the SCU and L2 bus.
- Accesses to all other locations are made to the L3 interconnect.
The MPU L2 cache controller contains a master connected to the system interconnect and a master connected to the SDRAM.
The MPU address space contains the following regions:
Description | Condition | Base Address |
End Address | Size |
---|---|---|---|---|
Boot ROM | Always visible | 0x00000000 |
0x000FFFFF |
1 MB |
SDRAM window | Always visible | 0x00100000 |
0xBFFFFFFF | 3047 MB (3 GB – 1 MB) |
HPS-to-FPGA | When remap.hps2fpga 15 is set. | 0xC0000000 | 0xFBFFFFFF | 348 KB |
System trace macrocell | Always visible | 0xFC000000 | 0xFFEFFFFF | 48 KB |
Debug access port | Always visible | 0xFF000000 | 0xFF1FFFFF | 2 MB |
Lightweight HPS-to-FPGA | Visible when remap.hps2fpga 15 is set. | 0xFF200000 | 0xFF3FFFFF | 2 MB |
Peripherals | Always visible | 0xFF400000 | 0xFFFCFFFF | 12096 KB |
Boot ROM | Always visible | 0xFFFD0000 | 0xFFFEBFFF | 112 KB |
SCU and L2 registers | Always visible | 0xFFFEC000 | 0xFFFEFFFF | 16 KB |
On-chip RAM | Always visible | 0xFFFF0000 | 0xFFFFFFFF | 64 KB |
Boot Region
The boot region is 1 MB, based at address 0x0. The boot region is visible to the MPU only when the L2 address filter start register is set to 0x100000. The L3 remap control register determines if the boot region is mapped to the on-chip RAM or the boot ROM.
The boot region is mapped to the boot ROM on reset. Only the lowest 64 KB of the boot region are legal addresses because the on-chip RAM and boot ROM are only 64 KB.
When the L2 address filter start register is set to 0, SDRAM obscures access to the boot region. This technique can be used to gain access to the lowest SDRAM addresses after booting completes.
SDRAM Window Region
The SDRAM window region provides access to a large, configurable portion of the 4 GB SDRAM address space. The address filtering start and end registers in the L2 cache controller define the SDRAM window boundaries.
The boundaries are megabyte-aligned. Addresses within the boundaries map to the SDRAM controller, which queues the read and write transactions for execution. Addresses that fall outside the boundaries route to the system interconnect, to access peripherals, bridges, and other HPS resources.
Addresses in the SDRAM window match addresses in the SDRAM address space. Thus, the lowest 1 MB of the SDRAM is not visible to the MPU unless the L2 address filter start register is set to 0.
HPS-to-FPGA Slaves Region
The HPS-to-FPGA slaves region provides access to slaves in the FPGA fabric through the HPS-to-FPGA bridge. Software can move the top of the SDRAM window by writing to the L2 address filter end register. If higher addresses are made available in the SDRAM window, part of the FPGA slaves region might be inaccessible to the MPU.
Lightweight HPS-to-FPGA Slaves Region
The lightweight FPGA slaves provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge.
Peripherals Region
The peripherals region is near the top of the address space. The peripheral region includes slaves connected to the L3 interconnect and L4 buses.
Boot ROM Region
The boot ROM is always mapped near the top of the address space, independent of the boot region contents.
SCU and L2 Registers Region
The SCU and L2 registers region provides access to internally-decoded MPU registers (SCU and L2).
On-Chip RAM Region
The on-chip RAM is always mapped near the top of the address space, independent of the boot region contents.