Visible to Intel only — GUID: sfo1410067682313
Ixiasoft
Visible to Intel only — GUID: sfo1410067682313
Ixiasoft
3.3.3.2. Main Clock Group
The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are derived from the main PLL. The main PLL is always sourced from the HPS_CLK1 pin of the device.
PLL |
Output Counter |
Clock Name |
Frequency |
Phase Shift Control |
---|---|---|---|---|
Main |
C0 |
|
osc1_clk to varies 7 |
No |
C1 |
|
osc1_clk to varies 7 |
No |
|
C2 |
|
osc1_clk/4 to mpu_base_clk/2 |
No |
|
C3 |
|
Up to 432 MHz |
No |
|
C4 |
|
Up to 250 MHz for the NAND flash controller and up to 200 MHz for the SD/MMC controller |
No |
|
C5 |
|
osc1_clk to 125 MHz for driving configuration and 100 MHz for the user clock |
No |
The counter outputs from the main PLL can have their frequency further divided by programmable dividers external to the PLL. Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example the clock transitions on cycle 15 of the divide‑by‑16 divider for the main C2 output and cycle 3 of the divide‑by‑4 divider for the main C0 output.
The following figure shows how each counter output from the main PLL can have its frequency further divided by programmable post‑PLL dividers. Green-colored clock gating logic is directly controlled by software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks.
The clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that a clean transition occurs, and can have the following control values changed dynamically by software write accesses to the control registers:
- PLL bypass
- PLL numerator, denominator, and counters
- External dividers
For these registers, hardware detects that the write has occurred and performs the correct sequence to ensure that a glitch-free transition to the new clock value occurs. These clocks can pause during the transition.
System Clock Name |
Frequency |
Constraints and Notes |
---|---|---|
|
Main PLL C0 |
Clock for MPU subsystem, including CPU0 and CPU1 |
|
mpu_clk/2 |
Clock for MPU level 2 (L2) RAM |
|
mpu_clk/4 |
Clock for MPU snoop control unit (SCU) peripherals, such as the general interrupt controller (GIC) |
|
Main PLL C1 |
Clock for L3 main switch |
|
l3_main_clk/2 |
Clock for L3 master peripherals (MP) switch |
|
l3_mp_clk or l3_mp_clk/2 |
Clock for L3 slave peripherals (SP) switch |
|
Main PLL C1 |
Clock for L4 main bus |
|
osc1_clk/16 to 100 MHz divided from main PLL C1 or peripheral PLL C4 |
Clock for L4 MP bus |
|
osc1_clk/16 to 100 MHz divided from main PLL C1 or peripheral PLL C4 |
Clock for L4 SP bus |
|
osc1_clk/4 to main PLL C2/2 |
Clock for CoreSight™ debug trace bus |
|
osc1_clk/16 to main PLL C2 |
Clock for CoreSight™ debug Trace Port Interface Unit (TPIU) |
|
osc1_clk to main PLL C2 |
Clock for the trace timestamp generator |
8 |
dbg_at_clk/2 or dbg_at_clk/4 |
Clock for Debug Access Port (DAP) and debug peripheral bus |
|
Main PLL C3 |
Quad SPI flash internal logic clock |
|
Main PLL C4 |
Input clock to flash controller clocks block |
|
osc1_clk to 100_MHz divided from main PLL C5 |
FPGA manager configuration clock |
|
osc1_clk to 100_MHz divided from main PLL C5 |
Auxiliary user clock to the FPGA fabric |