Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.3.2. Implementation Details

Table 57.   Cortex®-A9 MPCore* Processor Configuration This table shows the parameter settings for the Cortex®-A9 MPCore* .

Feature

Options

Cortex®-A9 processors

2

Instruction cache size per Cortex®-A9 processor

32 KB

Data cache size per Cortex®-A9 processor

32 KB

TLB size per Cortex®-A9 processor

128 entries

Media Processing Engine with NEON* technology per Cortex®-A9 processor21

Included

Preload Engine per Cortex®-A9 processor

Included

Number of entries in the Preload Engine FIFO per Cortex®-A9 processor

16

Jazelle DBX extension per Cortex®-A9 processor

Full

Program Trace Macrocell (PTM) interface per Cortex‑A9 processor

Included

Support for parity error detection22

Included

Master ports

Two

Accelerator Coherency Port

Included

21 Includes support for floating-point operations.
22 For a description of the parity error scheme and parity error signals, refer to the Cortex®-A9 Technical Reference Manual, available on the Arm* website (infocenter.arm.com).