Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.4.2. Implementation Details

The ACP is accessed by masters that require access to coherent memory. The ACP slave port can be accessed by the master peripherals of the L3 interconnect, as well as by masters implemented in the FPGA fabric (via the FPGA‑to‑HPS bridge).

The ACP ID mapper supports the following ID mapping modes:

  • Dynamic mapping
  • Fixed mapping

Software can select the ID mapping on a per‑ID basis. For input IDs that are configured for fixed mapping, there is a one‑to‑one mapping from input IDs to output IDs. When an input ID is configured for dynamic mapping, it is automatically mapped to an available output ID. The dynamic mode is more flexible because the hardware handles the mapping. The hardware mapping allows you to use one output ID for more than one input ID. Output IDs are assigned to input IDs on a first‑come, first‑served basis.

Note: If the number of differently configured masters exceeds the number available in fixed mode, you must use dynamic mode and ensure that the same AxUSER settings are used among all dynamic masters.

Out of the total of eight output IDs, only six are available to masters of the system interconnect. The first two output IDs (0 and 1) are dedicated to the Cortex®-A9 processor cores in the MPU subsystem, leaving the last six output IDs (2‑7) available to the ACP ID mapper. Output IDs 2‑6 support fixed and dynamic modes of operation while output ID 7 supports dynamic only.

The operating modes are programmable through accesses to the control and status registers in the ACP ID mapper. At reset time, the ACP ID mapper defaults to dynamic ID mapping for all output IDs except ID 2, which resets to a fixed mapping for the Debug Access Port (DAP) input ID.