Visible to Intel only — GUID: sfo1410069781353
Ixiasoft
Visible to Intel only — GUID: sfo1410069781353
Ixiasoft
21.3. I2C Controller Signal Description
All instances of the I2C controller connect to external pins through pin multiplexers. Pin multiplexing allows all instances to function simultaneously and independently. The pins must be connected to a pull-up resistors and the I2C bus capacitance cannot exceed 400 pF.
Pin Name |
Signal Width |
Direction |
Description |
---|---|---|---|
SCL |
1 bit |
Bidirectional |
Serial clock |
SDA |
1 bit |
Bidirectional |
Serial data |
Signal Name |
Signal Width |
Direction |
Description |
---|---|---|---|
i2c<#>_scl |
1 bit |
Input |
Incoming I2C clock source. This is the input SCL signal |
i2c<#>_out_clk |
1 bit |
Output |
Outgoing I2C clock enable. Output SCL signal. This signal is logically inverted and is synchronous to the HPS peripheral clock |
i2c<#>_sda |
1 bit |
Input |
Incoming I2C data. This is the input SDA signal. |
i2c<#>_out_data |
1 bit |
Output |
Outgoing I2C data enable. Output SDA signal. This signal is logically inverted and is synchronous to the HPS peripheral clock. |
The figure above shows the typical connection on the I2C interface in FPGA fabric with alt_iobuff.
For both I2C clock and data, external IO pins are open drain connection. When output enables i2c_out_data and i2c_out_clk are asserted, external signal will be driven to ground.