Visible to Intel only — GUID: sfo1410070096607
Ixiasoft
Visible to Intel only — GUID: sfo1410070096607
Ixiasoft
28.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges
Interface Name |
Description |
Associated Clock Interface |
---|---|---|
|
HPS-to-FPGA AXI master interface |
h2f_axi_clock |
|
HPS-to-FPGA lightweight AXI master interface |
h2f_lw_axi_clock |
The HPS-to-FPGA interface is a configurable data width AXI master (32-, 64-, or 128-bit) that allows HPS masters to issue transactions to the FPGA fabric.
The lightweight HPS-to-FPGA interface is a 32-bit AXI master that allows HPS masters to issue transactions to the FPGA fabric.
Both HPS-to-FPGA interfaces are AXI-3 compliant. The HPS-side AXI bridges manage clock crossing, buffering, and data width conversion where necessary.
Other interface standards in the FPGA fabric, such as connecting to Avalon-MM interfaces, can be supported through the use of soft logic adapters. The Platform Designer (Standard) system integration tool automatically generates adaptor logic to connect AXI to Avalon-MM interfaces.
Each AXI bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally. The exposed AXI interface operates on the same clock domain as the clock supplied by the FPGA fabric.