Visible to Intel only — GUID: sfo1410068397522
Ixiasoft
Visible to Intel only — GUID: sfo1410068397522
Ixiasoft
11.4.12. Debug Resets
The CoreSight* system uses several resets.
Arm* Reset Name |
Clock Source |
HPS Reset Signal Name |
Description |
---|---|---|---|
ATRESETn | Reset manager |
dbg_rst_n | Trace bus reset. It resets all registers in the ATCLK domain. |
nCTIRESET | Reset manager |
dbg_rst_n | CTI reset signal. It resets all registers in the CTICLK domain. In the HPS, there are four instances of CTI. All four use the same reset signal. |
DAPRESETn | Reset manager |
dbg_rst_n | DAP internal reset. It is connected to PRESETDBGn. |
PRESETDBGn | Reset manager |
dbg_rst_n | Debug APB* reset. Resets all registers clocked by PCLKDBG. |
HRESETn | Reset manager |
sys_dbg_rst_n | SoC-provided reset signal that resets all of the AMBA* on-chip interconnect. Use this signal to reset the DAP AHB* -Lite master port. |
PRESETSYSn | Reset manager |
sys_dbg_rst_n | Resets system APB* slave port of DAP. |
nCTMRESET | Reset manager |
dbg_rst_n | CTM reset signal. It resets all signals clocked by CTMCLK. |
nPOTRST | Reset manager |
tap_cold_rst_n | True power on reset signal to the DAP SWJ-DP. It must only reset at power-on. |
nTRST | JTAG interface |
nTRST pin |
Resets the DAP TAP controller inside the SWJ-DP. This signal is driven by the host using the JTAG connector. |
TRESETn | Reset manager |
dbg_rst_n | Reset signal for TPIU. Resets all registers in the TRACECLKIN domain. |
The ETR stall enable field (etrstallen) of the ctrl register in the reset manager controls whether the ETR is requested to stall its AXI* master interface to the L3 interconnect before a warm or debug reset.
The level 4 (L4) watchdog timers can be paused during debugging to prevent reset while the processor is stopped at a breakpoint.