Visible to Intel only — GUID: sfo1410070114195
Ixiasoft
Visible to Intel only — GUID: sfo1410070114195
Ixiasoft
29.2.1. Clock Interface
Platform Designer (Standard) generates the BFM clock for each clock input interface from the FPGA component. For the FPGA-to-HPS PLL reference clocks, specify the BFM reference clock frequency in the Reference clock frequency field in the HPS Clocks page when instantiating the HPS component in Platform Designer (Standard).
Interface Name |
BFM Instance Name |
---|---|
f2h_periph_ref_clock | f2h_periph_ref_clock_inst |
f2h_sdram_ref_clock | f2h_sdram_ref_clock_inst |
Platform Designer (Standard) generates the clock source BFM for each clock output interface from the HPS component. For HPS‑to‑FPGA user clocks, specify the BFM clock rate in the User clock frequency field in the HPS Clocks page when instantiating the HPS component in Platform Designer (Standard).
The HPS‑to‑FPGA TPIU generates a clock output to the FPGA, named h2f_tpiu_clock. In simulation, the clock source BFM also represents this clock output’s behavior. Also, the HPS‑to‑FPGA debug APB* interface generates a clock output to the FPGA, named h2f_debug_apb_clock.
Interface Name |
BFM Instance Name |
---|---|
h2f_user0_clock | h2f_user0_clock_inst |
h2f_user1_clock | h2f_user1_clock_inst |
h2f_user2_clock | h2f_user2_clock_inst |
h2f_tpiu_clock | h2f_tpiu_clock_inst |