Visible to Intel only — GUID: sfo1410067825516
Ixiasoft
Visible to Intel only — GUID: sfo1410067825516
Ixiasoft
6.3.3. Boot ROM Code
Registers in the system manager control whether the boot ROM code configures the pin multiplexing for boot pins after a warm reset. Set the warm-reset-configure-pin-multiplex for boot pins bit (warmrstcfgpinmux) of the boot ROM code register to enable or disable this control.
Registers in the system manager also control whether the boot ROM code configures the I/O pins used during the boot process after a warm reset. Set the warm reset configure I/Os for boot pins bit (warmrstcfgio) of the ctrl register to enable or disable this control.
When CPU1 is released from reset and the boot ROM code is located at the CPU1 reset exception address (for a typical case), the boot ROM reset handler code reads the address stored in the CPU1 start address register (cpu1startaddr) and passes control to software at that address.
There can be up to four preloader images stored in flash memory. The (initswlastld) register contains the index of the preloader's last image that is loaded in the on‑chip RAM.
The boot ROM software state register (bootromswstate) is a 32-bit general‑purpose register reserved for the boot ROM.
The following warmram related registers are used to configure the warm reset from on-chip RAM feature and must be written by software prior to the warm reset occurring.
Register |
Name |
Purpose |
---|---|---|
|
Enable |
Controls whether the boot ROM attempts to boot from the contents of the on-chip RAM on a warm reset. |
|
Data start |
Contains the byte offset of the warm boot CRC validation region in the on-chip RAM. The offset must be word-aligned to an integer multiple of four. |
|
Length |
Contains the length in bytes of the region in the on-chip RAM available for warm boot CRC validation. |
|
Execution offset |
Contains a 16-bit offset into the on-chip RAM that the boot code jumps to if the CRC validation succeeds. The boot ROM appends 0xFFFF to the upper 16-bits of this 32-bit register value when it is read. |
|
Expected CRC |
Contains the expected CRC of the region in the on-chip RAM. |
The number of wait states applied to the boot ROM's read operation is determined by the wait state bit (waitstate) of the ctrl register. After the boot process, software might require reading the code in the boot ROM. If software has changed the clock frequency of the l3_main_clk after reset, an additional wait state is necessary to access the boot ROM. Set the waitstate bit to add an additional wait state to the read access of the boot ROM. The enable safe mode warm reset update bit controls whether the wait state bit is updated during a warm reset.