Intel® Fortran Compiler Classic and Intel® Fortran Compiler Developer Guide and Reference

ID 767251
Date 11/07/2023
Public

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Document Table of Contents

mtune, tune

Performs optimizations for specific processors but does not cause extended instruction sets to be used (unlike -march).

Syntax

Linux:

-mtune=processor

Windows:

/tune:processor

Arguments

processor

Is the processor for which the compiler should perform optimizations. Possible values are:

generic

Optimizes code for the compiler's default behavior.

alderlake
amberlake
broadwell
cannonlake
cascadelake
coffeelake
cooperlake
goldmont
goldmont-plus
haswell
icelake-client (or icelake)
icelake-server
ivybridge
kabylake
rocketlake
sandybridge
sapphirerapids
silvermont
skylake
skylake-avx512
tigerlake
tremont
whiskeylake

Optimizes code for processors that support the specified Intel® processor or microarchitecture code name.

Keywords amberlake, coffeelake, icelake, kabylake, and whiskeylake are only available for ifort.

Keywords icelake-client and icelake are deprecated and may be removed in a future release.

core-avx2

Optimizes code for processors that support Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

core-avx-i

Optimizes code for processors that support the RDRND instruction, Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

corei7-avx

Optimizes code for processors that support Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

corei7

Optimizes code for processors that support Intel® SSE4 Efficient Accelerated String and Text Processing instructions. May also generate code for Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSE3, SSE2, SSE, and SSSE3 instructions.

atom

Optimizes code for processors that support MOVBE instructions, depending on the setting of option -minstruction (Linux) or /Qinstruction (Windows). May also generate code for SSSE3 instructions and Intel® SSE3, SSE2, and SSE instructions.

core2

Optimizes for the Intel® Core™2 processor family, including support for MMX™, Intel® SSE, SSE2, SSE3, and SSSE3 instruction sets.

Default

generic

Code is generated for the compiler's default behavior.

Description

This option performs optimizations for specific processors but does not cause extended instruction sets to be used (unlike -march).

The resulting executable is backwards compatible and generated code is optimized for specific processors. For example, code generated with -mtune=core2 or /tune:core2 runs correctly on 4th Generation Intel® Core™ processors, but it might not run as fast as if it had been generated using -mtune=haswell or /tune:haswell.

Code generated with -mtune=haswell (/tune:haswell) or -mtune=core-avx2 (/tune:core-avx2) will also run correctly on Intel® Core™2 processors, but it might not run as fast as if it had been generated using -mtune=core2 or /tune:core2.

This is in contrast to code generated with -march=core-avx2 or /arch:core-avx2, which will not run correctly on older processors such as Intel® Core™2 processors.

NOTE:

This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation. Offloading can only be enabled when using ifx.

NOTE:

ifx does not support compilation for 32-bit architectures; only processor values for 64-bit instruction sets may be specified for ifx.

Product and Performance Information

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.

Notice revision #20201201

IDE Equivalent

Visual Studio: Code Generation >Intel Processor Microarchitecture-Specific Optimization

Alternate Options

None

See Also