Reset_Mgr Address Map

Registers in the Reset Manager module
Module Instance Base Address End Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD110FF
Register Offset Width Access Reset Value Description
stat 0x0 32 RW 0x00000004 
Reset Status Register
miscstat 0x8 32 RW 0x00000000 
Timeout Status Register
hdsken 0x10 32 RW 0x00000000 
Handshake Enable
hdskreq 0x14 32 RW 0x00000000 
Handshake Request Register
hdskack 0x18 32 RW 0x00000000 
Handshake Acknowledge Register
hdskstall 0x1C 32 RW 0x00000000 
ETR Stall Status Register
mpumodrst 0x20 32 RW 0x00000000 
MPU Module Reset Register
per0modrst 0x24 32 RW 0xFFFFFFFF 
Peripheral 0 Module Reset Register
per1modrst 0x28 32 RW 0xFFFFFFFF 
Peripheral Module Reset Register
brgmodrst 0x2C 32 RW 0xFFFFFFFF 
Bridge Reset Register
coldmodrst 0x34 32 RW 0x00000000 
COLD Module Reset Register
dbgmodrst 0x3C 32 RW 0x00000000 
Debug Module Reset Register
tapmodrst 0x40 32 RW 0x00000000 
TAP Module Reset Register
brgwarmmask 0x4C 32 RW 0xFFFFFFFF 
Bridge Warm Mask Register
tststa 0x5C 32 RO 0x00000000 
Test Status
hdsktimeout 0x64 32 RW 0x00002800 
Hand Shake Time Out Value
mpul2flushtimeout 0x68 32 RW 0x00100000 
MPU L2 FLUSH Time Out Value Register
ocramload 0x80 32 RW 0x00000000 
On Chip RAM load done
mpurststat 0x4 32 RW 0x00000000 
MPU Reset Status
dbghdsktimeout 0x6C 32 RW 0x00100000 
L3NOC Debug CS_DAP Handshake Time Out Value