miscstat 

         The "miscstat" register contains bits that indicate the timeout event. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset.
After a cold reset is complete, all bits are reset to their reset value. A warm reset does not clear any of the bits in the "miscstat" register. These bits must be cleared by software writing 1 to the "miscstat" register.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

l3nocdbgtimeout

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mpul2flushtimeout

RW 0x0

Reserved

etrstalltimeout

RW 0x0

fpgahstimeout

RW 0x0

Reserved

sdrselfreftimeout

RW 0x0

miscstat Fields

Bit Name Description Access Reset
16 l3nocdbgtimeout 
A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway. Reset Manager performs this handshake with NOC when NOC is getting reset but debug logic does not get reset.
 RW 0x0
8 mpul2flushtimeout 
A 1 indicates that Reset Manager's handshake request to L2 Flush timed-out and the Reset Manager had to proceed with reset anyway.
 RW 0x0
3 etrstalltimeout 
A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0
2 fpgahstimeout 
A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0
0 sdrselfreftimeout 
A 1 indicates that Reset Manager's handshake request to the SDRAM Controller Subsystem timed out and the Reset Manager had to proceed with the warm/watchdog reset anyway.
 RW 0x0