hdskstall

         This register keeps the ETR stalled after a warm/watchdog reset occurs. If the ETR handshake is enabled in the bit field ETRSTALLEN of HDSKEN register, then the hardware will perform a handshake with the ETR before asserting a warm or watchdog reset. When the reset is complete, the hardware will keep the request signal to the ETR asserted to continue to stall it until software clears the HSDKSTALL register bit. 
Field is reset by a cold reset.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD11000`	`0xFFD1101C`

Size: 32

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`etrstallwarmrst` `RW 0x0`

hdskstall Fields

Bit	Name	Description	Access	Reset
0	`etrstallwarmrst`	If ETRSTALLEN bit field is 1 and Reset manager generates the handshake request to ETR, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master. Hardware leaves the ETR stalled after a warm or watchdog reset until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

etrstallwarmrst

If ETRSTALLEN bit field is 1 and Reset manager generates the handshake request to ETR, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master. Hardware leaves the ETR stalled after a warm or watchdog reset until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.

RW

0x0