brgwarmmask

         The "BRGWARMMASK"  register is used by software to mask the assertion of module reset signals on a warm reset. If the bit is 1, the module reset signal is asserted during a warm reset. If the bit is 0, the module reset signal is not asserted during a warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. 
 
All fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`i_rst_mgr_rstmgr`	`0xFFD11000`	`0xFFD1104C`

Size: 32

Offset: 0x4C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`ddrsch` `RW 0x1`	`f2ssdram2` `RW 0x1`	`f2ssdram1` `RW 0x1`	`f2ssdram0` `RW 0x1`	`fpga2soc` `RW 0x1`	`lwhps2fpga` `RW 0x1`	`soc2fpga` `RW 0x1`

brgwarmmask Fields

Bit	Name	Description	Access	Reset
6	`ddrsch`	Masks hardware sequenced warm reset for the DDR Scheduler in the NOC.	`RW`	`0x1`
5	`f2ssdram2`	Masks hardware sequenced warm reset for F2S_SDRAM2 Bridge.	`RW`	`0x1`
4	`f2ssdram1`	Masks hardware sequenced warm reset for F2S_SDRAM1 Bridge.	`RW`	`0x1`
3	`f2ssdram0`	Masks hardware sequenced warm reset for F2S_SDRAM0 Bridge	`RW`	`0x1`
2	`fpga2soc`	Masks hardware sequenced warm reset for FPGA2SOC Bridge	`RW`	`0x1`
1	`lwhps2fpga`	Masks hardware sequenced warm reset for LWHPS2FPGA Bridge	`RW`	`0x1`
0	`soc2fpga`	Masks hardware sequenced warm reset for SOC2FPGA Bridge.	`RW`	`0x1`