stat 

         The "stat" register contains bits that indicate the reset source. A field is 1 if its associated reset requester caused the reset. 
Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.
After a cold reset is complete, all bits are reset to their reset value, except the sdmcoldrst, debugrst, csdaprst and sdmporlastrst bits. sdmcoldrst, debugrst, csdaprst and sdmporlastrst are reset to their reset value on POR.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11000

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

csdaprst

RW 0x0

debugrst

RW 0x0

Reserved

l4wd3rst

RW 0x0

l4wd2rst

RW 0x0

l4wd1rst

RW 0x0

l4wd0rst

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mpu3rst

RW 0x0

mpu2rst

RW 0x0

mpu1rst

RW 0x0

mpu0rst

RW 0x0

Reserved

sdmlastporrst

RW 0x1

sdmwarmrst

RW 0x0

sdmcoldrst

RW 0x0

stat Fields

Bit Name Description Access Reset
25 csdaprst 
This bit indicates that CS DAP block has been reset. This bit is reset to its reset value on POR, not on warm or cold reset.
 RW 0x0
24 debugrst 
"debugrst" indicates if the debug reset has been asserted. This bit is reset to its reset value on POR, not on warm or cold reset.
 RW 0x0
19 l4wd3rst 
L4 Watchdog3 triggered a hardware sequenced warm reset.
 RW 0x0
18 l4wd2rst 
L4 Watchdog2 triggered a hardware sequenced warm reset.
 RW 0x0
17 l4wd1rst 
L4 Watchdog1 triggered a hardware sequenced warm reset.
 RW 0x0
16 l4wd0rst 
L4 Watchdog0 triggered a hardware sequenced warm reset.
 RW 0x0
11 mpu3rst 
MPU3 triggered a hardware sequenced warm reset.
 RW 0x0
10 mpu2rst 
MPU2 triggered a hardware sequenced warm reset.
 RW 0x0
9 mpu1rst 
MPU1 triggered a hardware sequenced warm reset.
 RW 0x0
8 mpu0rst 
MPU0 triggered a hardware sequenced warm reset.
 RW 0x0
2 sdmlastporrst 
SDM triggered last por reset. This bit is reset to its reset value on POR, not on warm or cold reset.
RW 0x1
1 sdmwarmrst 
SDM triggered warm reset.
 RW 0x0
0 sdmcoldrst 
SDM triggered cold reset. This bit is reset to its reset value on POR, not on warm or cold reset.
 RW 0x0