GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

4.2.2.1. Two-segment Interface Example

The following example illustrates how to use the Interlaken IP TX and RX multisegment interface.

TX Multisegment

This example shows the expected behavior of multisegment Interlaken IP at the TX user interface during a 65 byte packet transfer in two-segment interleave mode.
Figure 14. TX Multisegment User Interface Example

The IP only supports two segment chunks in any cycle. Therefore, you need only two-bit eob, two sets of eopbits and channel numbers.

In this example, in cycle 0, the data occupies segment 1 and 0. In cycle 1, the segment 1 occupies data from the previous cycle and the second segment of data occupies in segment 0. Only one burst starts in cycle 0. In sob= 2'b10, the sob [1] refers to the start of a burst at word 7. The eopbits0 and eopbits1 indicates no end of packet because eopbits [3] and eopbits1[3]=0. Only the channel number for the first segment chunk is valid, which is 8'hAB. This channel number corresponds to the burst indicated by sob[1]=1'b1. A channel number is always associated to a start of a burst.

In cycle 1, in sob= 2'b01, the burst in the first segment continues the second segment of the last cycle. No sob[1] set in this cycle. The sob[0]=1 of the second segment refers to the start of a burst at word 3. The packet (first segment chunk) ends in this cycle, hence eopbits=4'b1000 indicating the last word contains eight bytes. The eob=1'b1 is for the first segment chunk. The eopbits1 indicates no EOP because eopbits1[3]=0. Only the channel number for the second segment chunk is valid, which is 'hCD.

One burst ends in cycle 2. In sob= 2'b00, the burst in the first segment continues the second segment of the last cycle. No sob[1] is set in this cycle. The packet ends in this cycle, hence, eopbits=4'h1000, indicates the last word containing eight bytes. The eob=1'b1 is for the first segment chunk.

RX Multisegment

This example shows the behavior of a multisegment Interlaken IP at the RX user interface.
Figure 15. RX Multisegment User Interface Example
Level Two Title