GTS Interlaken Intel® FPGA IP User Guide

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ID 819200
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Interlaken Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. GTS Interlaken IP Registers 7. GTS Interlaken FPGA IP User Guide Archives 8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide
1. About the GTS Interlaken Intel® FPGA IP x
1.1. GTS Interlaken IP Features 1.2. GTS Interlaken IP Device Family Support 1.3. Device Speed Grade Support 1.4. GTS Interlaken IP Performance and Resources 1.5. GTS Interlaken IP Round-Trip Latency 1.6. GTS Interlaken IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel FPGA IPs 2.2. Generated File Structure 2.3. Specifying the GTS Interlaken IP Parameters and Options 2.4. Reference and System PLL Clock for Your IP Design 2.5. Simulating the GTS Interlaken IP 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel FPGA IPs x
2.1.1. Intel FPGA Evaluation Mode
3. Parameter Settings x
3.1. Analog Parameters for GTS IPs
4. Functional Description x
4.1. Datapath Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Datapath Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multisegments
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Examples
4.2.2. Multisegments x
4.2.2.1. Two-segment Interface Example
5. Interface Signals x
5.1. GTS Interlaken IP Clock and Reset Interface Signals 5.2. GTS Interlaken IP Transmit User Interface Signals 5.3. GTS Interlaken IP Receive User Interface Signals 5.4. GTS Interlaken IP Management Interface Signals 5.5. GTS Interlaken Link and Miscellaneous Signals 5.6. GTS Interlaken IP Reconfiguration Signals
1. About the GTS Interlaken Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. GTS Interlaken IP Registers
7. GTS Interlaken FPGA IP User Guide Archives
8. Document Revision History for GTS Interlaken Intel FPGA IP User Guide

5.3. GTS Interlaken IP Receive User Interface Signals

Table 23.  GTS Interlaken IP Receive User Interface Signals
Signal Name Width (Bits) I/O Direction Available In Description
irx_chan 8 Output Interlaken mode Receive logic channel number for the first segment chunk. The IP core supports up to 256 channels. The Interlaken IP core samples this value only when a bit of irx_sop or irx_sob is high and irx_num_valid has a non-zero value.
irx_chan1 8 Output Interlaken mode Receive logic channel number for the second segment chunk. The IP core supports up to 256 channels. This signal is used in DUALsegment mode.

The Interlaken IP core samples this value only when a bit of irx_sob[0] is high and irx_num_valid of the second segment chunk has a non-zero value.

irx_num_valid Variable Output Interlaken mode

Indicates the number of valid 64-bit words in the current packet in the current data symbol. The width of the irx_num_valid depends on the parameter external_words.

  • If external_words=4, then width=3*2 bits.
  • If external_words=8, then width=4*2 bits.
irx_eob 1 Output Interlaken mode Indicates the end of the burst (EOB) for the first segment chunk.

When irx_eopbits has valid value of 4’b1xxx or 4’b0001, the irx_eob is valid too, but not vice-versa.

Whenever parameter RX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter RX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

irx_eob1 1 Output Interlaken mode Indicates the end of the burst (EOB) for the second segment chunk.

Only DUAL segment interface defines this signal.

When irx_eopbits1 has valid value of 4’b1xxx or 4’b0001, the irx_eob1 is valid too, but not vice-versa.

Whenever parameter RX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter RX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

irx_eopbits 4 Output Interlaken mode Specifies the number of bytes at the end of packet (EOP) for the first segment chunk. Indicates whether the current data symbol contains the EOP with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.
IP core sets the value of irx_eopbits as following:
  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
irx_eopbits1 4 Output Interlaken mode Specifies number of bytes at the end of packet (EOP) for the second segment chunk. This signal is used in DUAL segment mode.
You must set the value of irx_eopbits1 as following:
  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
irx_sob Variable Output Interlaken mode

Indicates the current data symbol contains the start of a burst (SOB). If the IP core is in Interleaved mode (RX_PKTMOD_ONLY = 0), you are responsible for providing this start of the burst signal. If the IP core is in Packet mode (RX_PKTMOD_ONLY = 1), the IP core ignores this signal.

The IP core samples the irx_chan signal during this cycle.

  • [0] - single segment with number of words = 4
  • [1] - single segment with number of words = 8
  • [1:0] - Dual segment

This signal has the following valid values:

Using two segment as example. This signal has the following valid values:

[1] : indicates SOB for the first segment(segment 1)

[0]: indicate SOB for the second segment(segment 0).

For example:

If number of words = 8, Number of segments=2, rx_num_valid [7:4] = 4, rx_num_valid [4:0]=4. The second segment will start at word [3], sob [1:0]=11 (binary).

If number of words = 8, Number of segments=2, rx_num_valid [7:4] = 1, rx_num_valid [4:0]=1. The second segment will still start at word [3], sob [1:0]=11 (binary).

irx_sop Variable Output Interlaken mode

Indicates the current data symbol on irx_din_words contains the start of a packet (SOP).

  • [0] - single segment with number of words = 4
  • [1] - single segment with number of words = 8
  • [1:0] - Dual segment

The segment order is defined as {segment1, segment0} with segment 1 at MSB.

Using two segment as an example. This signal has the following valid values:

[1] : indicates SOP for the first segment(segment 1)

[0]: indicate SOP for the second segment(segment 0).

For example:

If number of words = 8, Number of segments=2,

rx_num_valid [7:4] = 4, rx_num_valid [4:0]=4. The second segment will start at word[3], sop[1:0]=11 (binary).

If number of words = 8, Number of segments=2, rx_num_valid [7:4] = 1, rx_num_valid [4:0]=1. The second segment will still start at word [3], sop [1:0]=11 (binary).

irx_dout_words Variable Output Interlaken mode The 64-bit words of received data (one data symbol). The width of the irx_dout_words depends on the parameter external_words.
  • If external_words=4, then width=256 bits.
  • If external_words=8, then width=512 bits.

The first and last data word is in [511:448] and [63:0] respectively. When irx_ num_valid has the value of zero, you should ignore irx_dout_words.

irx_calendar N * 16 Output Interlaken mode Multiple pages (16 bits per page) of calendar input bits. The value is the in-band flow control bits from N control words on the incoming Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with rx_usr_clk, although it is not part of the user data transfer protocol.
irx_err 1 Output Interlaken mode Indicates an errored packet. This signal is valid only when irx_eob is asserted.
irx_err1 1 Output Interlaken mode Indicates an errored packet in second segment chunk. This signal is valid only when irx_eob1 is asserted.

This signal is only valid in DUAL mode.
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