Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

3. Performance Monitor IP Functional Description

The Performance Monitor (PMON) IP works as a pass-through bridge for an AXI4 connection between IPs. It accepts the AXI4 signals from a manager and sends commands to the AXI4 subordinate without modifying anything on the interface.

The following figure illustrates the PMON IP implementation.

Figure 1. PMON Implementation Block Diagram

The PMON IP instantiates two main blocks:

  • AXI4 Unit Monitor. The unit monitor provides AXI4 sink and source interfaces through which traffic passes. The unit monitor does not interfere with or modify any signals on the interface; it simply monitors the interface and collects metrics based on the control status register (CSR) configuration.
  • Global Monitor. The global monitor coordinates between multiple unit monitors in the system.

The User AXI4 Initiator acts as a manager and the AXI4 Responder functions as a subordinate.

Note:
  • In the current release, the PMON IP supports only the AXI4 interface protocol.
  • In the current release, the PMON IP supports only a one global to one unit monitor configuration.

Section Content
AXI4 Traffic Limitations

Level Two Title