Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery PMON_UDIS_L: Offset: Block Stride * 8h Size 32 PMON_UDIS_H: Offset: (Block Stride * 8h) + 4h Size 32 PMON_UCADR_L: Offset: (Block Stride * 8h) + 8h Size 32 PMON_UCADR_H: Offset: (Block Stride * 8h) + 0Ch Size 32 PMON_UIDT_L: Offset: (Block Stride * 8h) + 10h Size 32 PMON_UIDT_H: Offset: (Block Stride * 8h) + 14h Size 32 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

5.4.4. Unit Discovery

PMON_UDIS_L: Offset: Block Stride * 8h Size 32

Table 27.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
NumCntr 7:0 RO 8’h8 Number of counter control registers paired with counter data registers in this unit.
UnitCntrCtrlAdr_offset 15:8 RO 8’h10 8b offset from Unit Control Address (PMON_UCADR) to first Counter Control register. (PMON_UCCTRL).
CntrWidth 23:16 RO 8’h30 Number of bits in the counter data register, default 48bit Data Counter register.
UnitCntrDataAdr_offset 31:24 RO 8’h50 8b offset from Unit Control Address (PMON_UCADR) to first Counter Data register (PMON_UCDATA).

PMON_UDIS_H: Offset: (Block Stride * 8h) + 4h Size 32

Table 28.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
UnitStatAdr_offset 7:0 RO 8’h8 8b offset from Unit Control Address (PMON_UCADR) to Unit Status register (PMON_USTS).
Reserved 28:8 RO 21’b0 Reserved
AccessType 31:29 RO 3’b001

Unit State is addressed through

000 – MSR space

001 – MMIO space

010 – PCICFG space

PMON_UCADR_L: Offset: (Block Stride * 8h) + 8h Size 32

Table 29.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
UCAddress_L 31:0 RO 32’h118 Base Address[31:0] to Unit Control and Status Register & Counter Control and Counter Data registers PMON_UCTRL, PMON_USTS, PMON_UCCTRL, PMON_UCDATA.

PMON_UCADR_H: Offset: (Block Stride * 8h) + 0Ch Size 32

Table 30.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
UCAddress_H 31:0 RO 32’b0 Base Address[63:32] to Unit Control and Status Register & Counter Control and Counter Data registers PMON_UCTRL, PMON_USTS, PMON_UCCTRL, PMON_UCDATA.

PMON_UIDT_L: Offset: (Block Stride * 8h) + 10h Size 32

Table 31.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
UnitType 15:0 RO 16’b0

Unit type with which this PMON block is associated.

Each Unit of a Unit Type will have the same events available or capture and same protocol-specific performance monitoring HW available.

0 = AXI-4
UnitID 31:16 RO 16’b0

Which # of Unit Type

For cases where there are more than 1 instance of a particular Unit, this IDs the specific PMON block for the Unit Type. This value is passed in from the Unit ID parameter.

PMON_UIDT_H: Offset: (Block Stride * 8h) + 14h Size 32

Table 32.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
GblStatPosition 15:0 RO 16’b0 16b field to tell SW which bit in the Global Status belongs to this PMON unit block.
Reserved 31:16 RV 16’b0 Reserved
Level Two Title