Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers PMON_GDIS_L: Offset: I_PMON_BAR:0000h Size 32 PMON_GDIS_H: Offset: I_PMON_BAR:0004h Size 32 PMON_GCADR_L: Offset: I_PMON_BAR:0008h Size 32 PMON_GCADR_H: Offset: I_PMON_BAR:000Ch Size 32 I_PMON_GSOFF_L: Offset: I_PMON_BAR:0010h Size 32 I_PMON_GSOFF_H: Offset: I_PMON_BAR:0014h Size 32 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

5.4.1. Global Discovery Registers

PMON_GDIS_L: Offset: I_PMON_BAR:0000h Size 32

I_PMON_BAR = 0

Table 16.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
UnitType 7:0 RO 8’b0 Global Block Unit Type.
BlockStride 15:8 RO 8’h20

The length of each stride represents the amount of space reserved for each discovery block. From the I_PMON_BAR, base address, SW will need to stride through MaxBlocks-1 times from the base address to identify all discovery state.

Block Stride is counted in 64 bit registers. When parametrized this should be set based on the size of the largest unit monitor (the one with the most counters initialized).
MaxBlocks 25:16 RO 10'h001

Max Blocks

The number of strides (0 for the global discovery node) SW will need to make through the address space to ensure that all the unit discovery state for the domain has been found. This should equal the number of unit monitors.
Reserved 31:26 RV 6’h00 Reserved bits.

PMON_GDIS_H: Offset: I_PMON_BAR:0004h Size 32

Table 17.   AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Reserved 28:0 RV 29’b00 Reserved bits.
AccessType 31:29 RO-V 3’b001

Global State is addressed through

000 – MSR space

001 – MMIO space

010 – PCICFG space

Others - Reserved

PMON_GCADR_L: Offset: I_PMON_BAR:0008h Size 32

Table 18.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
GCAddress_L 31:0 RO 32’h18 Base Address[31:0] to Global Control and Status Register – I_PMON_GCTRL, I_PMON_GSTS

PMON_GCADR_H: Offset: I_PMON_BAR:000Ch Size 32

Table 19.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
GCAddress_H 31:0 RO 32’b0 Base Address[63:32] to Global Control and Status Register – I_PMON_GCTRL, I_PMON_GSTS

I_PMON_GSOFF_L: Offset: I_PMON_BAR:0010h Size 32

Table 20.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
GblStatAdr_offset 7:0 RO 8’h08 Global Counter Status Address. 8b offset from the Global Control Address (I_PMON_GCADR) to the global counter status register (I_PMON_GSTS).
NumBlockStatus 23:8 RO 16’b0 Status bits allocated to track overflows. For cases there are more than 64 status bits, SW should divide this value by 64 to calculate the number of contiguously addressed counter status registers.
Reserved 31:24 RV 8’b0 Reserved.

I_PMON_GSOFF_H: Offset: I_PMON_BAR:0014h Size 32

Table 21.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Reserved 31:0 RV 32’b0 Reserved.
Level Two Title