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1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions
5.4.1. Global Discovery Registers
5.4.2. Global Control Registers
5.4.3. Global Status Registers
5.4.4. Unit Discovery
5.4.5. Unit Control Registers
5.4.6. Unit Status Registers
5.4.7. Counter Control Registers
5.4.8. Data Registers
I_PMON_UCDATA_L[j] : PMON_UCADR + UnitCntrDataAdr_offset + (j*8h) Size 32
I_PMON_UCDATA_H[j] : PMON_UCADR + UnitCntrDataAdr_offset + (j*8h) + 4h Size 32
5.4.9. AXI4 Event Support
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5.4.8. Data Registers
I_PMON_UCDATA_L[j] : PMON_UCADR + UnitCntrDataAdr_offset + (j*8h) Size 32
Field | Bit | Attribute | Default | Description |
---|---|---|---|---|
Evnt_Count_L | 32:0 | RW-V | 32’b0 | (CntrWidth-1)-bit Performance Event Counter. Default to 48 bit wide counter. |
I_PMON_UCDATA_H[j] : PMON_UCADR + UnitCntrDataAdr_offset + (j*8h) + 4h Size 32
Field | Bit | Attribute | Default | Description | |
---|---|---|---|---|---|
Evnt_Count_H | 15:0 | RW-V | 16’b0 | (CntrWidth-1)-bit Performance Event Counter. Default to 48 bit wide counter. | |
Reserved | 31:16 | RV | 16’h0 | Reserved. |