Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers I_PMON_UCCTL_L[j] PMON_UCADR + UnitCntrCtrlAdr_offset + (j*8h) Size 32 I_PMON_UCCTL_H[j] PMON_UCADR + UnitCntrCtrlAdr_offset + (j*8h) + 4h Size 32 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

5.4.7. Counter Control Registers

I_PMON_UCCTL_L[j] PMON_UCADR + UnitCntrCtrlAdr_offset + (j*8h) Size 32

Table 37.  AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Evnt_Sel 7:0 RW-V 8’b0

Event Select

Minimum field to select which of the available events should be recorded in the paired data register. Additional bits in the control register may also be required to select from the available events.
Umask 15:8 RW-V 8’b0 Each bit corresponds to a subevent of an event chosen by Event Select. Not all events have sub events. If using an event without subevents treat this as reserved and 0 must be written to these bits.
Reserved 16 RV 1’b0 Reserved.
Cntr_Rst 17 RW/1S/V 1’b0

Counter Reset

Write 1 to clear the corresponding counter. When counter is cleared, this bit will revert to 0.
Edge 18 RW-V 1’b0

Edge Detect

When set to 1, rather than measuring the event in each cycle it is active, the corresponding counter will increment when a 0 to 1 transition (i.e. rising edge) is detected. This increment is by the counter increment of that cycle.

When 0, the counter will increment in each cycle that the event is asserted.
Reserved 19 RV 1’b0 Reserved.
Frz_On_Ov 20 RW-V 2’b0

Freeze on Overflow

When an overflow is detected from this Counter register, a PMON overflow indication is sent to the global status.

This bit will tell the global control whether it should assert the global freeze for all counters in the same domain.
Reserved 22:21 RV 2’b0 Reserved.
Invert 23 RW-V 1’b0

Invert comparison against Threshold

0 - comparison will be ‘is event increment >= threshold?’.

1 - comparison is inverted - ‘is event increment < threshold?’
Thresh 31:24 RW-V 8’b0

Threshold on Counter Increment.

Threshold is used, along with the invert bit, to compare against the incoming increment value that will be added to the counter. The counter will increment by 1 when using this filter.

For events that increment by more than 1 per cycle, if the threshold is set to a value greater than 1, the data register will accumulate instances in which the event increment is >= threshold.

I_PMON_UCCTL_H[j] PMON_UCADR + UnitCntrCtrlAdr_offset + (j*8h) + 4h Size 32

Table 38.   AXI-Lite: ACLK, RESETn
Field Bit Attribute Default Description
Max 0 RW-V 1’b0

Compare against counter and replace

When set to 1 rather than the counter incrementing by the incoming increment value, it will be compared against the value currently stored in counter. If it is greater than the value currently stored in the counter, then the counter will be replaced by the increment.
Reserved 31:1 RV 31’b0 Reserved.
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