Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

2. Introduction to the Performance Monitor (PMON) IP

The Performance Monitor (PMON) FPGA IP is a synthesizable soft logic IP for measuring performance on an interface. It consists of control and status registers that allow you to configure, track, and filter performance metrics. The PMON supports Agilex™ 5 and Agilex™ 7 M-Series devices.

The PMON IP is built around a system of event-based tracking logic that combines a variety of basic and derived metrics for monitoring. It provides automated discovery mechanisms and user-modifiable software for maximum metric-tracking flexibility.

You can use the Performance Monitor to calculate various performance metrics such as the following:

  • Efficiency. Available for read and write and each subchannel, helping to tune for maximum performance.
  • Latency. Available for read and write via outstanding transaction counts.
  • Transaction counts. Available for each subchannel with various ready valid combination states to identify channel behavior.
  • Traffic duration. Available for read and write, total and individual subchannel.
  • Burst data. Can be used to compare response and data transactions compared to address channels.
  • Back pressure. Available for each subchannel, helping to identify bottlenecks in the system.
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