Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

Download PDF
ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

3.1. AXI4 Traffic Limitations

The AXI4 interface has the following limitations for collecting performance metrics.
  • Not all metrics can be provided in a single run of the application.
  • Supports a maximum of 65,533 outstanding transactions for accurate latency metrics.
  • Does not support maximum or minimum latency (rather the maximum filter applied to latency metrics provides the maximum number of outstanding transactions).
  • Requires no traffic gaps on read or write channels greater than 65,535 cycles to measure efficiency accurately.
  • Requires at least 2 transactions on an AXI4 subchannel to measure efficiency for the subchannel.
  • Counters are 48 bits; variable sizes are not currently supported.
  • Does not support metric configuration mid traffic.
  • Reading metrics mid traffic provides an approximation rather than an exact value.
  • Supports a maximum of 64 monitors in the system.
  • Requires symmetry in RDATA and WDATA widths as well as ARID and AWID widths.
Level Two Title