GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency 5.9. Dual Simplex Support 5.10. Analog Parameter Settings 5.11. Transceiver Toolkit
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

2. Overview of the GTS JESD204C Intel® FPGA IP

The GTS JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface for transferring data between data converters (such as ADCs or DACs) and FPGA devices. The primary advantage of JESD204C lies in its ability to streamline interface wiring while significantly increasing data rates compared to earlier standards like JESD204B. This makes JESD204C particularly well-suited for wireless communications, especially in 5G networks, where it is integral to base stations and infrastructure requiring high-speed data transfer between RF ADC/DAC components and signal processing units such as FPGAs. Additionally, JESD204C is widely employed in high-performance data acquisition systems, test and measurement equipment, and automotive advanced driver assistance systems (ADAS), supporting key applications such as lidar and radar in autonomous driving technologies.

This unidirectional serial interface runs at a maximum data rate of 17.16 Gbps for Agilex™ 5 E-Series and 28.1 Gbps for Agilex™ 5 D-Series. This protocol offers higher bandwidth, low I/O count and supports scalability in both number of lanes and data rates.

The GTS JESD204C Intel® FPGA IP addresses multi-device synchronization using Subclass 1 to achieve deterministic latency.

The GTS JESD204C Intel® FPGA IP supports Simplex (TX-only, RX-only), Duplex (TX/RX—shared PHY, same data rates), and Dual Simplex (TX/RX—Independent PHY, different data rates) modes.

The Intel® FPGA IP is a unidirectional protocol where interfacing to ADC utilizes the transceiver RX path and interfacing to DAC utilizes the transceiver TX path.

The GTS JESD204C TX and RX cores run on a link clock with 64-bit data width, which reduces the area utilization.

The Intel® FPGA IP incorporates:

  • Media access control (MAC)—data link layer (DLL) and transport layer (TL) blocks that control the link states.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

The transport layer (TL) in the MAC controls the assembling and disassembling of the frames.

Figure 1.  GTS JESD204C Duplex Functional Block Diagram
Figure 2.  GTS JESD204C TX-only Functional Block Diagram
Figure 3.  GTS JESD204C RX-only Functional Block Diagram

Section Content
Release Information
Device Family Support
GTS JESD204C Intel FPGA IP Features
Performance and Resource Utilization

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