GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency 5.9. Dual Simplex Support 5.10. Analog Parameter Settings 5.11. Transceiver Toolkit
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

5.9. Dual Simplex Support

In cases where the TX IP and RX IP use different parameter settings or the number of TX and RX channels needed differs, you can use a dual simplex (DS) group to maximize your transceiver channel usage.

For a DS group, you may create an independent simplex TX IP (with one or more channels) and an independent simplex RX IP (with one or more channels) and use the Dual Simplex Assignment Editor to fit them into the duplex channel. Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for more information.

To create a DS group:
  1. Generate GTS JESD204C TX and RX simplex IP.
  2. Provide location of each simplex IP in a DS group relative to the starting channel location in the DS Assignment Editor. To do this, open the Dual Simplex Assignment Editor in Quartus® Prime by selecting Assignments > Dual Simplex (DS) Assignment Editor.
  3. Assign your individual simplex IPs to a dual simplex (DS) group by right-clicking your IP component under the IP > Click Create Instance in… > Select or create a new DS group.
    Figure 23. DS Assignment Editor

    The DS Assignment Editor does a quick legality check (protocol level and attribute level) to see if the simplex IPs assigned to a dual simplex group are compatible. If the simplex IPs are not compatible, error messages will be prompted.

  4. After assigning simplex IPs to a DS group, save the assignments. When you save the DS group, the QSF assignments are added automatically to the project QSF. For example:
  5. Run the HSSI Dual Simplex IP Generation in the Compilation Dashboard to obtain a new DS IP:
  6. Connect the generated DS IP to the rest of your design logic:
Note:

The Dual Simplex support for the GTS JESD204C IP in current release of the Quartus® Prime software is limited to:

  • JESD204C TX IP and JESD204C RX IP only.
  • Compilation flow only supported up to Synthesis.
  • Simulation only supported for PHY only JESD204C wrapper with up to 4 channels.
  • TX IP and RX IP must share the same data rate, PLL/CDR reference clock frequency, and number of lanes per converter device (L).
  • Relative Offset in the DS group needs to be 0.
  • A DS group only contains one JESD204C TX IP and one JESD204C RX IP
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