GTS JESD204C Intel® FPGA IP User Guide

ID 813959
Date 4/01/2024
Public
Document Table of Contents

2.4. Performance and Resource Utilization

Table 7.   GTS JESD204C Intel® FPGA IP Performance
Device Family PMA Speed Grade Core Speed Grade Maximum Data Rate (Gbps)
FCLK_MULP = 1 FCLK_MULP = 2
Agilex™ 5 0 –1 17.16 17.16
–2 17.16 17.16
–3 17.16 17.16

The following table lists the estimated resource utilization data of the GTS JESD204C IP. These results are obtained using the Quartus® Prime software targeting the Agilex™ 5 device.

The variations for resource utilization are configured with the following parameter settings:

Table 8.  Parameter Settings to Obtain the Resource Utilization Data
Parameter Setting
JESD204C Wrapper Both Base and PHY
JESD204C Subclass 1
Data Rate 17.16 Gbps
Reference Clock Frequency 260 MHz
Enable Scrambler (SCR) On
Enable Error Code Correction (ECC_EN) Off
Table 9.   GTS JESD204C IP Resource Utilization for Agilex™ 5 Devices
Variants L M F FCLK_MULP WIDTH_MULP ALM ALUT Logic Register M20K
TX 4 8 6 1 4 2348 2792 3018 8
4 8 6 2 2 2592 3157 3436 8
4 8 4 1 2 2226 2704 2558 8
4 8 4 2 1 2718 3277 3560 8
RX 2 8 12 1 2 2015 2925 2773 12
2 8 12 2 1 1833 2781 2489 12
1 2 8 1 1 932 1403 1152 5
1 2 8 2 1 940 1414 1156 5
1 4 24 1 1 1242 1537 1441 6
1 4 24 2 1 1068 1539 1445 6
3 2 4 1 2 2336 3441 2652 12
3 2 4 2 1 2356 3493 2910 12