1

Input

Transceiver reference clock signal.

1

Input

This clock is equal to the RX data rate divided by 66. Generated from the same PLL as rxframe_clk.

1

Input

This signal is synchronous with rxlink_clk. Frequency is equal or multiplied by 2 of rxlink_clk. Generated from the same PLL as rxlink_clk.

1

Input

1

Input

Avalon® memory-mapped interface clock.

Acknowledgment indicator of the state of j204c_rx_rst_n.

1

Input

Transceiver reconfiguration clock. During duplex mode, both TX and RX share the same reconfiguration pins.

Input

1

Input

Active-low asynchronous reset signal for MAC LL, PHY, and TL.

Input

Active-low asynchronous reset signal for RX Avalon® memory-mapped interface.

This signal deasserts synchronously to rx_avs_clk.

Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins.

Intel recommends that you tie this signal to tx_avs_rst_n.

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

L

Input

Differential high speed serial input data. The clock is recovered from the serial data stream.

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig_xcvr_clk.

1

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

log2(L) +18

Input

Each transceiver lanes address is 18 bits wide. The upper bits are lane select.

This signal is synchronous with reconfig__xcvr_clk.

32

Output

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

32

Input

During duplex mode, both TX and RX share the same reconfiguration pins.

This signal is synchronous with reconfig__xcvr_clk.

Byte enable signal. If byteenable[3:0] is 4’b1111, uses 32-bit Dword; otherwise uses byte access.

This signal is synchronous with reconfig__xcvr_clk.

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

This signal is synchronous with rx_avs_clk.

10

Input

For Avalon® memory-mapped slave, each slave access is based on byte-based offset. For example, address = 0 selects the first four bytes of the slave register and the address = 4 selects the next four bytes of the slave register space.

This signal is synchronous with rx_avs_clk.

32

Input

32-bit data for write transfers.

This signal is synchronous with rx_avs_clk.

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the j204c_rx_avs_readdata[31:0] signal to be in use.

This signal is synchronous with rx_avs_clk.

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the j204c_rx_avs_writedata[31:0] signal to be in use.

This signal is synchronous with rx_avs_clk.

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

This signal is synchronous with rx_avs_clk.

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The GTS JESD204C Intel® FPGA IP ties this signal to 0 to return the data in the access cycle.

This signal is synchronous with rx_avs_clk.

M*S*N*WIDTH_MULP

Output

The minimum data width = M*S*N. This signal is synchronous to rxframe_clk. Indicates the converter samples that is processed by TL.

This signal indicates a 64-bit user data (per lane) at rxlink_clk clock rate, where 8 octets are packed into a 64-bit data width per lane. The data format is big endian.

If L=1 and M*S*N*WIDTH_MULP=64, the first octet is located at bit[63:56], followed by bit[55:48], and the last octet is bit[7:0]. If more than one lane is instantiated, Lane 0 data is always located in the upper 64-bit. Data lane L’s data is located at bit[63:0], with the first octet position for lane L is at bit[63:56].

M*S*WIDTH_MULP*CS

Output

Control bits that were inserted as part of CS parameter.

This signal is synchronous to rxframe_clk.

1

Output

Indicates whether the data to the application layer is valid or invalid. The Avalon® streaming sink interface in the RX core cannot be backpressured and assumes that the data is always valid on every cycle when the j204c_rx_avst_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

This signal is synchronous to rxframe_clk.

1

Input

Indicates that the Avalon® streaming sink interface in the application layer is ready to accept data. The Avalon® streaming sink interface asserts this signal on the JESD204C transport state of USER_DATA phase. The ready latency is 0.

This signal is synchronous to rxframe_clk.

L

Output

Indicates when CRC error is detected on previous multiblock.

This signal is synchronous to rxlink_clk.

L*6

L*18

Output

Indicates a 6/18-bit user command (per lane) at rxlink_clk clock rate. The data format is big endian.

If more than one lane is instantiated, lane 0 data is always located at the upper 18 bits or 6 bits of data. Lane L is located at bit[17:0] or bit[5:0], with the first command bit position for lane L at bit[17] or bit[5].

This signal is synchronous to rxlink_clk.

If CRC-12 is enabled, the width is L*6. If standalone command channel, the width is L*18.

1

Output

This signal is synchronous to rxlink_clk.

Indicates whether the command from the link layer is valid or invalid when the j204c_rx_cmd_ready signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

This signal is synchronous to rxlink_clk.

Indicates that the transport or application layer is ready to accept command. The application layer interface asserts this signal on the JESD204C link/transport state of USER_DATA phase. The ready latency is 0.

1, L

Output

This signal is synchronous to rxlink_clk.

Indicates when parity error is detected.

• Width is 1 if you enable single lane mode.
• Width is L if you disable single lane mode.

1

Input

SYSREF signal for JESD204C Subclass 1 implementation.

For Subclass 0 mode, tie-off this signal to 0.

1

Output

Indicates sync header lock.

This signal is synchronous to rxlink_clk.

1

Output

Indicates EMB lock.

This signal is synchronous to rxlink_clk.

Output

Indicates that all EMB blocks of all the lanes in a GTS JESD204C IP instance are aligned.

1

Output

Indicates that all lanes in a GTS JESD204C IP instance are aligned.

Input

For multilink synchronization, input the j204c_rx_dev_emblock_align signals from all the GTS JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

1

Input

For multi-device synchronization, input the j204c_rx_dev_lane_align signals from all the GTS JESD204C IP instances to an AND gate and connect the AND gate output to this signal.

For single device, connect the j204c_rx_dev_lane_align signal back to this signal.

This signal is synchronous to rxlink_clk.

4

Output

Indicates the number of active lanes for the link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

8

Output

Indicates the number of octets per frame. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

8

Output

Indicates the number of converters for the link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

2

Output

Indicates the number of control bits per sample. The transport layer uses this signal as a compile-time parameter.

5

Output

Indicates the converter resolution. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

5

Output

Indicates the total number of bits per sample. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer uses this signal as a compile-time parameter.

1

Output

Indicates the high density data format. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

Output

LEMC period. The transport layer uses this signal as a compile-time parameter.

This signal is synchronous to rx_avs_clk.

2

Output

This signal is synchronous to rx_avs_clk.

• 0—No test mode
• 1—Invalid
• 2—TX2RX_GB loopback mode enabled (64 bit loopback)
• 3—Invalid

1

Output

Asynchronous signal.

Interrupt pin for the GTS JESD204C Intel® FPGA IP.

Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

This input is valid when the 66/64 gearbox is available.

Synchronous to rxphy_clk.

Multiplexed with the RX gearbox input when the TX2RX_GB loopback mode is enabled to connect to TX IP in the duplex setup (same signal name) for the TX2RX loopback function.

If L > 0, MSB of this bus is mapped to Lane 0. LSB is mapped to Lane L-1.