GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency 5.9. Dual Simplex Support 5.10. Analog Parameter Settings 5.11. Transceiver Toolkit
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

5.2.1. GTS JESD204C TX Reset Sequence

Figure 9.  GTS JESD204C TX Reset Sequence

The descriptions below correspond to the GTS JESD204C TX Reset Sequence:

  1. The user logic asserts the GTS JESD204C IP and configuration reset to the GTS JESD204C IP TX, j204c_tx_avs_rst_n = 0, j204c_tx_rst_n = 0, and reconfig_xcvr_reset = 1.
    Note: If you assert j204c_tx_avs_rst_n and reconfig_xcvr_reset, j204c_tx_rst_n is required to be asserted as well. You can opt to assert j204c_tx_rst_n without asserting j204c_tx_avs_rst_n and reconfig_xcvr_reset.
  2. The user logic deassert j204c_tx_avs_rst_n and reconfig_xcvr_reset and perform configurations of the PHY and IP. At the same, wait for IOPLL to lock.
  3. After all relevant PHY channels are fully in reset, the IP core asserts j204c_tx_rst_ack_n = 1 to the user logic. Knowing the relevant channels are in proper reset states, the user logic can release the reset to the IP core when possible (j204c_tx_rst_n = 1). Use j204c_tx_rst_ack_n as an indicator to deassert j204c_tx_rst_n = 1.
  4. The user logic deasserts the IP reset (j204c_tx_rst_n = 1).
  5. The IP core deasserts j204c_tx_rst_ack_n = 1 to indicate that reset sequence is complete.
  6. The IP asserts j204c_tx_avst_ready = 1. The GTS JESD204C TX IP core is operational.
  7. At any time when you require a reset to the MAC and PHY, you must wait for j204c_tx_rst_ack_n = 1. Assertion of j204c_tx_rst_n = 0 resets the MAC and PHY in the IP core.
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