GTS JESD204C Intel® FPGA IP User Guide

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ID 813959
Date 12/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C Intel® FPGA IP User Guide 2. Overview of the GTS JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C Intel® FPGA IP 6. GTS JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer Intel® FPGA IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C Intel® FPGA IP x
5.1. Configuring the GTS Reset Sequencer Intel® FPGA IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency 5.9. Dual Simplex Support 5.10. Analog Parameter Settings 5.11. Transceiver Toolkit
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
1. About the GTS JESD204C Intel® FPGA IP User Guide
2. Overview of the GTS JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C Intel® FPGA IP
6. GTS JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Document Revision History for the GTS JESD204C Intel® FPGA IP User Guide

2.3. GTS JESD204C Intel® FPGA IP Features

The GTS JESD204C Intel® FPGA IP is the latest IP from Intel that supports the GTS JESD204C protocol. This IP is not backwards compatible and does not support JESD204B protocol.

Table 6.  Brief Information about the GTS JESD204C Intel® FPGA IP

Features

Description

Protocol Features
  • Joint Electron Device Engineering Council (JEDEC) JESD204C standard 2017
  • Device subclass:
    • Subclass 0—No deterministic latency
    • Subclass 1—Uses SYSREF signal to support deterministic latency
Core Features
  • Data rate of up to 28.1 Gbps for Agilex™ 5 devices
  • Single or multiple lanes (up to 8 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E = 1 to 32
  • Supports F = 1 to 256 octets per frame
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multi-device synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • Interrupts and error handling support
  • 64b/66b encoding
  • Scrambling/descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for control and status registers (CSR)
  • Dynamic generation of simulation testbench
  • Optional support for ECC M20K DCFIFO
  • Support for Transceiver Toolkit for PMA using embedded Native PHY Debug Master Endpoint (NPDME)
  • Options for sync header configurations
    • CRC-12
    • Standalone command channels
Limitations No FEC support
Typical Application
  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment
Device Family Support
  • Agilex™ 5 FPGA devices
Design Tools
  • Platform Designer parameter editor in the Quartus® Prime Pro Edition software for design creation and compilation

  • Timing Analyzer in the Quartus® Prime software for timing analysis

  • QuestaSim* and VCS* MX simulator software for design simulation or synthesis
Level Two Title