MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The Quartus® Prime software generates the design example files in the following folders:

Figure 5. Directory Structure for MIPI CSI-2 Intel® FPGA IP Design Example
Table 3.  Generated Files in Quartus® Prime Folder and File Description
File Description
quartus The folder that contains Quartus® Prime output files, including Quartus® Prime compilation reports.
csi2_dphy_sys.qpf IntelQuartus Prime project file.
csi2_dphy_sys.qsf IntelQuartus Prime Qsf assignment file.
Table 4.  Generated Files in RTL Folder and File Description
Directory / File Description
rtl The folder for each synthesizable component including Platform Designer (Standard) generated IPs.
csi2_dphy_sys.qsys Qsys subsystem file that contains CSI-2 RX and DPHY configuration.
rtl/csi2_dphy_sys The folder that contains Platform Designer generated folder.
csi2_dpy_sys/synth/csi2_dphy_sys.v Top level subsystem wrapper Verilog file.
rtl/ip The folder that contains all IP files and IPs Platform Designer generated folder.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rx.ip IP file for MIPI CSI-2 RX core.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx.ip IP file for MIPI CSI-2 TX core.
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy.ip IP file for MIPI D-PHY core.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0.ip IP file Reset Release.
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge.ip IP file Clock Bridge for AXI4S Clock.
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge.ip IP file Clock Bridge for DPHY Clock.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rxsynth/csi2_dphy_sys_csi2_rx.v MIPI CSI-2 RX IP wrapper Verilog file.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx/synth/csi2_dphy_sys_csi2_tx.v MIPI CSI-2 TX IP wrapper Verilog file.
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy/synth /csi2_dphy_sys_mipi_dphy.v MIPI D-PHY IP wrapper Verilog file.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0/synth/ csi2_dphy_sys_csi2_reset_release_0.v Reset Release IP wrapper Verilog file.
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge/synth/ csi2_dphy_sys_axi_clock_bridge.v AXI4S Clock Bridge IP wrapper Verilog file.
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge/synth/ csi2_dphy_sys_dphy_clock_bridge.v DPHY Clock Bridge IP wrapper Verilog file.
Table 5.  Generated Files in Simulation Folder and File Description
Directory / File Description
ed_sim/ed_sim_tb.sv Top-level testbench file.
ed_sim/dut_wrapper.sv Wrapper around MIPI CSI-2 TX, RX and PPI Loopback.
ed_sim/cfg_pkg.sv SystemVerilog package containing generated IP Core parameters.
ed_sim/sim.spd File used by Quartus ip-make-simscript.
ed_sim/hdl/ Contains Encrypted Verification IP files.
ed_sim/sim/aldec Contains Riviera simulator script.
aldec/sim.do Script for Riviera simulation.
aldec/rivierapro_setup.tcl Setup file for Riviera simulation.
ed_sim/sim/mentor Contains Mentor simulator script.
sim.do Script for Modelsim simulation.
msim_setup.tcl Setup file for Modelsim simulation.
ed_sim/sim/synopsys/vcs Contains Synopsys VCS simulator script.
vcs/sim.sh Script for VCS simulation
vcs/vcs_setup.sh Setup Script for VCS simulation.
ed_sim/sim/synopsys/vcsmx Contains Synopsys VCSMX simulator script.
vcsmx/sim.sh Script for VCS simulation
vcsmx/vcsmx_setup.sh Script for VCSMX simulation.
vcsmx/synopsys_sim_setup.sh Setup file for VCSMX simulation.
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