1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 5. Interface Signals 6. Configuration Registers 7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Clocking and Reset Sequence 3.2. Timing Constraints 3.3. Operation Speed Switching 3.4. USXGMII 3.5. Fmax Requirement
3.1. Clocking and Reset Sequence x
3.1.1. Clocking 3.1.2. Reset Sequence
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.9. Transceiver Status and Reconfiguration Signals

Table 23.  Transceiver Status and Reconfiguration Signals
Signal Name Direction Width Description PHY Configurations
Transceiver status signals
rx_is_lockedtodata Output 1 Asserted when the CDR is locked to the RX data. All
Transceiver reconfiguration signals
reconfig_clk Input 1 Reconfiguration signals connected to the reconfiguration block. All
reconfig_reset Input 1
reconfig_address Input

18
reconfig_be Input 4
reconfig_write Input 1
reconfig_read Input 1
reconfig_writedata Input 32
reconfig_readdata Output 32
reconfig_readdata_valid Output 1
reconfig_waitrequest Output 1
Level Two Title