1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

3.4. Operation Speed Switching

Table 11.  Operating Speed Switching Methodology
PHY Configuration Speed Switch Methodology
2.5G —
1G/2.5G

1G to 2.5G switching is not supported for 1G/2.5G MBGASE-T.

10M/100M/1G/2.5G

Switching between (10M/100M/1G) and (2.5G): Transceiver reconfiguration with manual speed switching via CSR reconfiguration block available external to the PHY. The PHY must be reset after speed switch.

Switching within (10M/100M/1G): Use SGMII AN or CSR configuration

Note: Switching between 10M/100M/1G and 2.5G is not supported.
10M/100M/1G/2.5G/5G/10G (USXGMII)

Manual speed switching via CSR available inside the PHY.
Table 12.  Supported Operating Speed
PHY Configuration Features 10M 100M 1G 2.5G 5G 10G
2.5G Protocol — — — 1000BASE-X @ 2.5x — —
Transceiver Data Rate — — — 3.125 Gbps — —
MAC Interface — — — 16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz — —
1G/2.5G Protocol — — 1000BASE-X 1000BASE-X @ 2.5x — —
Transceiver Data Rate — — 1.25 Gbps 3.125 Gbps — —
MAC Interface — — 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz 16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz — —
10M/100M/1G/2.5G Protocol SGMII

100x data replication

 SGMII

10x data replication

 1000BASE-X/SGMII 1000BASE-X @ 2.5x — —
Transceiver Data Rate 1.25 Gbps 1.25 Gbps 1.25 Gbps 3.125 Gbps — —
MAC Interface 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable high 1/100 cycles

 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable high 1/10 cycles

 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable always high

 16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz

Clock enable always high

 — —
10M/100M/1G/2.5G/5G/10G (USXGMII) Protocol 10GBASE-R

1000x data replication

 10GBASE-R

100x data replication

 10GBASE-R

10x data replication

 10GBASE-R

4x data replication

 10GBASE-R

2x data replication

 10GBASE-R

No data replication
Transceiver Data Rate 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps
MAC Interface 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal
Level Two Title