1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/07/2024
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.6. GMII Signals

Table 20.  GMII Signals
Signal Name Direction Width Description PHY Configurations
TX GMII signals (16-bit)
gmii16b_tx_d Input 16 TX data from the MAC for 1G and 2.5G.
  • 2.5G (MGBASE)
  • 1G/2.5G (MGBASE)
  • 1G/2.5G/10G
  • 10M/100M/1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
gmii16b_tx_en Input 2 TX valid from the MAC for 1G and 2.5G.
gmii16b_tx_err Input 2 TX error from MAC for 1G and 2.5G.
tx_clkena Output 1 TX clock enable for SGMII 10M/100M operating speeds.
  • 10M/100M/1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
gmii16b_tx_latency Output 22 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.
This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.
Note: This is the latency output when ENABLE_ADAPTER is 1. The final latency value takes this value and multiply with the serial rate and divide by 20 clock period.
  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
RX GMII signals (16-bit)
gmii16b_rx_d Output 16 RX data to the MAC for 1G and 2.5G.
  • 10M/100M/1G/2.5G (MGBASE)
gmii16b_rx_err Output 2 RX error to MAC for 1G and 2.5G.
gmii16b_rx_dv Output 2 RX valid to MAC for 1G and 2.5G.
rx_clkena Output 1 RX clock enable for SGMII 10M/100M operating speeds.
gmii16b_rx_latency Output 22 The latency of the PHY excluding the PMA block on the RX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.
This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.
Note: This is the latency output when ENABLE_ADAPTER is 1. The final latency value takes this value and multiply with the serial rate and divide by 20 clock period.
  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
TX GMII signals (8-bit)
gmii8b_tx_clkin Input 1 Input clock for GMII (8-bit).
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G(MGBASE)
gmii8b_tx_clkout Output 2 GMII TX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M.
gmii8b_tx_rst_n Input 1 Reset signal for the GMII8B adapter on the TX path.
gmii8b_mac_tx_d Input 8 TX data from MAC for 1G and 2.5G.
gmii8b_mac_txen Input 1 TX valid from MAC for 1G and 2.5G.
gmii8b_mac_txer Input 1 TX error from MAC for 1G and 2.5G.
RX GMII signals (8-bit)
gmii8b_rx_clkout Output 1 GMII RX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G(MGBASE)
gmii8b_rx_rst_n Input 1 Reset signal for the GMII8B adapter on the RX path.
gmii8b_mac_rx_d Output 8 RX data to MAC for 1G and 2.5G.
gmii8b_mac_rxdv Output 1 RX valid to MAC for 1G and 2.5G.
gmii8b_mac_rxer Output 1 RX error to MAC for 1G and 2.5G.
gmii8b_mac_col Output 1 GMII/MII collision detection to MAC.
gmii8b_mac_crs Output 1 GMII/MII carrier sense detection to MAC.
gmii8b_mac_speed Input 2 MAC speed indication.
Level Two Title