1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.4. Avalon Memory-Mapped Interface Signals

Table 18.  Avalon Memory-Mapped Interface Signals
Signal Name Direction Width Description PHY Configurations
csr_address Input 5, 11 Use this bus to specify the register address to read from or write to. The width is:
  • 5 bits for 2.5G and 1G/2.5G configurations.
  • 11 bits for 1G/2.5G/10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
 All
csr_read Input 1 Assert this signal to request a read operation.
csr_readdata Output 16, 32 Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_write Input 1 Assert this signal to request a write operation.
csr_writedata Input 16, 32 Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 1G/2.5G/10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_waitrequest Output 1 When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
  • When you have requested for a read or write, keep the control signals to the Avalon® memory-mapped interface constant while this signal is asserted. The request is complete when it is deasserted.
  • This signal can be high or low during idle cycles and reset. Therefore, your application must not make any assumption of its assertion state during these periods.
Level Two Title