1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

3.1. Architecture

Figure 6. Architecture of the 2.5G, 1G/2.5G, 10M/100M/1G/2.5G (MGBASE-T) Configuration
  • The MGBASE-T configuration for Agilex™ 5 devices supports the following variants:
    • 2.5G
    • 1G/2.5G
    • 10M/100M/1G/2.5G
  • The MGBASE-T configuration is clocked at 156.25 MHz to achieve a maximum data rate of 2.5G.
  • The MGBASE-T configuration includes the following interfaces:
    • 10M/100M—MII, 4 bit
    • 1G/2.5G—GMII, 8 bit or 16 bit
    • 10M/100M/1G/2.5G—GMII, 8 bit or 16 bit
  • The MGBASE-T configuration supports the following line rates:
    • 1.25 Gbps for 10M/100M/1G
    • 3.125 Gbps for 2.5G
  • The MGBASE-T configuration uses PMA direct mode.
  • The 1G/2.5G MGBASE-T configuration mode supports IEEE 1588v2 feature.
  • GMII 8-bit adapter is used with HPS EMAC configuration along with the MGBASE-T mode.
Figure 7. Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
  • The NBASE-T/USXGMII configuration for Agilex™ 5 devices supports 10M/100M/1G/2.5G/5G/10G variant.
  • The NBASE-T/USXGMII configuration is clocked at 312.5 MHz to achieve a maximum data rate of 10G.
  • The NBASE-T/USXGMII configuration includes the following interfaces:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
  • The NBASE-T/USXGMII configuration supports the following line rates:
    • 10 Gbps for all USXGMII data rates
  • The NBASE-T/USXGMII configuration uses PCS direct mode.