1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

3.1. Architecture

The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY).

Figure 6. Architecture of the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design examples using the Low Latency Ethernet 10G MAC Intel® FPGA IP.
The IP includes the following interfaces:
  • Datapath client-interface:
    • 2.5G —GMII, 8 bits
    • 1G/2.5G—GMII, 16 bits
    • 1G/2.5G/10G—XGMII, 64 bits
    Note:
    The 1G/2.5G and 1G/2.5G/10G variants support 10M/100M rates when SGMII is enabled.
  • Management interface— Avalon® memory-mapped interface host slave interface for PHY management.
  • Datapath ethernet interface with the following available options:
    • 10G—Single 10.3125 Gbps serial ink
    • 2.5G—Single 3.125 Gbps serial ink
    • 10M, 100M, 1G—Single 1.25Gbps SGMII serial ink
  • GMII 8-bit adapter is used with the HPS EMAC configuration along with the MGBASE mode. It provides 8-bit GMII interface (gmii8b) to the MAC for 1G/2.5G. For 10M/100M, the data-width is only 4 bits (MII). The least significant 4-bit of the 8-bit data interface is used for the data transfer.
Figure 7. Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
  • Datapath client-interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
  • Management interface— Avalon® memory-mapped interface host slave interface for PHY management.
  • Datapath ethernet interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—Single 10.3125 Gbps serial link.
Level Two Title