Security Overview for SDM-Based FPGA Devices

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ID 794424
Date 9/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA Device Security Overview 2. Device Security Features Overview 3. Device Security Resources 4. Revision History for the Security Overview for SDM-based FPGA Devices
2. Device Security Features Overview x
2.1. Hardware Root of Trust 2.2. Authentication 2.3. Attributes 2.4. Configuration Bitstream Encryption 2.5. Platform Attestation 2.6. Cryptographic Services 2.7. Physical Anti-Tamper Monitoring 2.8. Secure Debug
1. FPGA Device Security Overview
2. Device Security Features Overview
3. Device Security Resources
4. Revision History for the Security Overview for SDM-based FPGA Devices

2.5. Platform Attestation

Platform attestation helps the operator of one or many Altera® FPGA systems verify the identity and configuration of the FPGAs. The SDM applies the authentication and encryption policies embedded in SDM fuses and the bitstream, then provides certificates of its identity and signed measurements of the configured bitstream to an external verifier. The external verifier compares the reports from the SDM to known device identity certificates and known configuration bitstream measurements generated by Quartus® Prime Pro Edition software. Platform attestation can help FPGA system operators determine whether devices are currently operating in the expected state over time.

Level Two Title