Security Overview for SDM-Based FPGA Devices

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ID 794424
Date 9/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA Device Security Overview 2. Device Security Features Overview 3. Device Security Resources 4. Revision History for the Security Overview for SDM-based FPGA Devices
2. Device Security Features Overview x
2.1. Hardware Root of Trust 2.2. Authentication 2.3. Attributes 2.4. Configuration Bitstream Encryption 2.5. Platform Attestation 2.6. Cryptographic Services 2.7. Physical Anti-Tamper Monitoring 2.8. Secure Debug
1. FPGA Device Security Overview
2. Device Security Features Overview
3. Device Security Resources
4. Revision History for the Security Overview for SDM-based FPGA Devices

2. Device Security Features Overview

Altera® designs FPGAs that provide advanced security features in order to help you meet your requirements for implementing a secured system. This section provides a high-level overview and description of these security features. Not all security features are available on all devices.


Section Content
Hardware Root of Trust
Authentication
Attributes
Configuration Bitstream Encryption
Platform Attestation
Cryptographic Services
Physical Anti-Tamper Monitoring
Secure Debug

Level Two Title