Security Overview for SDM-Based FPGA Devices

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ID 794424
Date 9/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA Device Security Overview 2. Device Security Features Overview 3. Device Security Resources 4. Revision History for the Security Overview for SDM-based FPGA Devices
2. Device Security Features Overview x
2.1. Hardware Root of Trust 2.2. Authentication 2.3. Attributes 2.4. Configuration Bitstream Encryption 2.5. Platform Attestation 2.6. Cryptographic Services 2.7. Physical Anti-Tamper Monitoring 2.8. Secure Debug
1. FPGA Device Security Overview
2. Device Security Features Overview
3. Device Security Resources
4. Revision History for the Security Overview for SDM-based FPGA Devices

2.7. Physical Anti-Tamper Monitoring

The SDM can help detect changes in the operating environment that may indicate an attempt to influence, modify, or reverse-engineer system behavior and automatically respond to those changes. The SDM includes many passive anti-tamper features that continuously operate; active physical anti-tamper features operate on parameters you specify. The SDM active physical anti-tamper feature monitors configuration clock frequency, voltage of SDM and FPGA power rails, and SDM temperature. The SDM provides a bidirectional interface to logic in the FPGA fabric to notify the logic of a tamper event detection and to allow the logic to initiate a tamper response.

Level Two Title