Visible to Intel only — GUID: byd1675738160151
Ixiasoft
Visible to Intel only — GUID: byd1675738160151
Ixiasoft
2.2.2. Multicycle Custom Instruction Timing
On the first clock cycle of the custom instruction execution, the processor asserts the active high enable port. Simultaneously, the data0, data1, and alu_result ports have valid values and remain valid for the duration of the custom instruction execution. The enable signal is asserted for a single clock cycle.