AN 977: Nios® V Processor Custom Instruction

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ID 773194
Date 4/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Designing with Intel® Quartus® Prime and Platform Designer 5. Document Revision History for AN 977: Nios® V Processor Custom Instruction
1. Nios® V Processor Custom Instruction Overview x
1.1. Implementing Custom Instruction 1.2. Implementing Custom Instruction Logic Block 1.3. Implementing Custom Instruction Software
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types 2.2. Multicycle Custom Instructions 2.3. Extended Custom Instruction 2.4. External Interface Custom Instructions
2.2. Multicycle Custom Instructions x
2.2.1. Multicycle Custom Instruction Ports 2.2.2. Multicycle Custom Instruction Timing 2.2.3. Implementing Combinational Custom Instruction
2.3. Extended Custom Instruction x
2.3.1. Extended Custom Instruction Timing
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software C Macro 3.2. Custom Instruction Assembly Language Interface 3.3. Custom Instruction Word Format
3.2. Custom Instruction Assembly Language Interface x
3.2.1. Custom Instruction Assembly Language Syntax
3.3. Custom Instruction Word Format x
3.3.1. Selector and Extension Indexes 3.3.2. ALU Switch 3.3.3. User-defined Immediate
4. Designing with Intel® Quartus® Prime and Platform Designer x
4.1. Interface Signals 4.2. Custom Instruction Manager 4.3. Custom Instruction Subordinate
4.1. Interface Signals x
4.1.1. alu_result port 4.1.2. ctrl port
4.2. Custom Instruction Manager x
4.2.1. Hardware Interfaces Table 4.2.2. Software C-Macro Table
4.3. Custom Instruction Subordinate x
4.3.1. Writing the Custom Instruction HDL File 4.3.2. Opening the Component Editor 4.3.3. Specifying the Custom Instruction Component Type 4.3.4. Displaying the Custom Instruction Block Symbol 4.3.5. Adding the Custom Instruction HDL File 4.3.6. Configuring the Custom Instruction Parameter Type 4.3.7. Setting Up the Custom Instruction Interfaces 4.3.8. Saving and Adding the Custom Instruction 4.3.9. Generating and Compiling the Processor System
1. Nios® V Processor Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Designing with Intel® Quartus® Prime and Platform Designer
5. Document Revision History for AN 977: Nios® V Processor Custom Instruction

2.2.1. Multicycle Custom Instruction Ports

Table 2.  Multicycle Custom Instruction Ports
Port Name Direction Required? Description
clk Input Yes System clock.
reset Input Yes Synchronous reset.
data0[31:0] Input Optional 2 Input operand to custom instruction logic block (Source Register 1).
data1[31:0] Input Optional2 Input operand to custom instruction logic block (Source Register 2).
alu_result[31:0] Input Optional2 Input operand to custom instruction logic block (ALU Switch result).
ctrl[31:0] Input Optional2 Custom instruction word. Reserved for other use.
enable Input Yes Custom instruction logic block enables.
done Output Yes Indicator to the completion of the custom instruction execution.
result[31:0] Output Optional2 Result of the custom instruction.

The Nios® V processor system clock feeds the custom logic block’s clk port. The Nios® V processor system reset feeds the active high reset port. The reset port asserts only when the whole Nios® V processor system resets.

If you assert the enable port, the Nios® V processor custom instruction logic receives input thru the data0, data1, and alu_result ports, and drives the result to its result port. The processor considers the result as valid when the logic block asserts the done port. The ctrl port delivers the full instruction word to the logic block for other use.
Figure 4. Multicycle Custom Instruction Block Diagram
2 Use only if the custom instruction requires the port.
Level Two Title