AN 977: Nios® V Processor Custom Instruction

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ID 773194
Date 4/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Designing with Intel® Quartus® Prime and Platform Designer 5. Document Revision History for AN 977: Nios® V Processor Custom Instruction
1. Nios® V Processor Custom Instruction Overview x
1.1. Implementing Custom Instruction 1.2. Implementing Custom Instruction Logic Block 1.3. Implementing Custom Instruction Software
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types 2.2. Multicycle Custom Instructions 2.3. Extended Custom Instruction 2.4. External Interface Custom Instructions
2.2. Multicycle Custom Instructions x
2.2.1. Multicycle Custom Instruction Ports 2.2.2. Multicycle Custom Instruction Timing 2.2.3. Implementing Combinational Custom Instruction
2.3. Extended Custom Instruction x
2.3.1. Extended Custom Instruction Timing
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software C Macro 3.2. Custom Instruction Assembly Language Interface 3.3. Custom Instruction Word Format
3.2. Custom Instruction Assembly Language Interface x
3.2.1. Custom Instruction Assembly Language Syntax
3.3. Custom Instruction Word Format x
3.3.1. Selector and Extension Indexes 3.3.2. ALU Switch 3.3.3. User-defined Immediate
4. Designing with Intel® Quartus® Prime and Platform Designer x
4.1. Interface Signals 4.2. Custom Instruction Manager 4.3. Custom Instruction Subordinate
4.1. Interface Signals x
4.1.1. alu_result port 4.1.2. ctrl port
4.2. Custom Instruction Manager x
4.2.1. Hardware Interfaces Table 4.2.2. Software C-Macro Table
4.3. Custom Instruction Subordinate x
4.3.1. Writing the Custom Instruction HDL File 4.3.2. Opening the Component Editor 4.3.3. Specifying the Custom Instruction Component Type 4.3.4. Displaying the Custom Instruction Block Symbol 4.3.5. Adding the Custom Instruction HDL File 4.3.6. Configuring the Custom Instruction Parameter Type 4.3.7. Setting Up the Custom Instruction Interfaces 4.3.8. Saving and Adding the Custom Instruction 4.3.9. Generating and Compiling the Processor System
1. Nios® V Processor Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Designing with Intel® Quartus® Prime and Platform Designer
5. Document Revision History for AN 977: Nios® V Processor Custom Instruction

1.1. Implementing Custom Instruction

Nios® V processor custom instructions are custom logic blocks adjacent to the arithmetic logic unit (ALU) in the processor’s datapath.

Nios® V processor custom instructions are based on the RISC-V R-type instruction format, and provides support for four unique opcodes. Leveraging the funct7[6:4] in the custom instruction, each opcode is further associated with eight custom logic blocks. In total, you can have up to 32 custom logic blocks connected to a single Nios® V processor. Logic block connections on the Nios® V processor are exposed as Nios V Custom Instruction Manager interfaces, and are defined using the Custom Instructions Hardware Interfaces Table in the Nios® V processor IP parameterization.

Figure 2. Custom Logic Blocks
The following steps show how you can implement and use custom instructions with the Nios® V processor:
  1. When you implement the custom instructions in the Nios® V processor system, each custom operation must associate with its unique selector index (opcode and funct7[6:4]).
  2. The selector index allows the software to specify the desired operation from among up to 32 custom logic blocks.
  3. In the Platform Designer, you can define one or more selector index using the Custom Instructions Hardware Interfaces Table. Each defined selector index would be presented as a Nios V Custom Instruction Manager interface on the Nios® V processor.
  4. You can define custom instruction software C macros for software deployment in system.h using the Custom Instructions Hardware Interfaces Table in the Nios V IP parameterization. An accompanying GDB debug memonics file for the defined software C macros is generated by Platform Designer for use by the Ashling* RiscFree* IDE for Intel® FPGAs.
Note: You can have up to 128 custom instructions in a single custom logic block using the extended custom instructions. For example, if you instantiate all 32 logic blocks, you can have a maximum of 4096 custom instructions connected to a single Nios® V processor.
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