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4.3.1. Writing the Custom Instruction HDL File
4.3.2. Opening the Component Editor
4.3.3. Specifying the Custom Instruction Component Type
4.3.4. Displaying the Custom Instruction Block Symbol
4.3.5. Adding the Custom Instruction HDL File
4.3.6. Configuring the Custom Instruction Parameter Type
4.3.7. Setting Up the Custom Instruction Interfaces
4.3.8. Saving and Adding the Custom Instruction
4.3.9. Generating and Compiling the Processor System
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1.2. Implementing Custom Instruction Logic Block
The Nios® V processor supports three types of custom instructions:
- Multicycle
- Extended
- External Interface
Figure 3. Nios® V Processor Custom Instruction Logic Block Interface
Custom Instruction logic blocks consists of a Nios® V Processor Custom Instruction Subordinate interface. The figure above shows all the ports in the Nios V Custom Instruction Subordinate interface that communicates with the Nios® V processor.
- clk
- reset
- data0[31:0]
- data1[31:0]
- alu_result[31:0]
- ctrl[31:0]
- enable
- result[31:0]
- done
All the ports can accommodate all custom instruction types. The figure above also shows a conduit interface to the external logic. The interface to external logic allows you to include a custom interface to system resources outside of the Nios® V processor datapath.
Nios® V processor custom instructions requires the clk, reset, enable and done ports. The custom instruction logic provides a result based on the inputs provided by the Nios® V processor. When the enable port is asserted, the Nios® V processor custom instruction logic receives inputs on its data0, data1, and alu_result ports and outputs the result to its result port. When the logic block asserts the done port, the processor considers the result valid.