AN 977: Nios® V Processor Custom Instruction

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ID 773194
Date 4/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Designing with Intel® Quartus® Prime and Platform Designer 5. Document Revision History for AN 977: Nios® V Processor Custom Instruction
1. Nios® V Processor Custom Instruction Overview x
1.1. Implementing Custom Instruction 1.2. Implementing Custom Instruction Logic Block 1.3. Implementing Custom Instruction Software
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types 2.2. Multicycle Custom Instructions 2.3. Extended Custom Instruction 2.4. External Interface Custom Instructions
2.2. Multicycle Custom Instructions x
2.2.1. Multicycle Custom Instruction Ports 2.2.2. Multicycle Custom Instruction Timing 2.2.3. Implementing Combinational Custom Instruction
2.3. Extended Custom Instruction x
2.3.1. Extended Custom Instruction Timing
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software C Macro 3.2. Custom Instruction Assembly Language Interface 3.3. Custom Instruction Word Format
3.2. Custom Instruction Assembly Language Interface x
3.2.1. Custom Instruction Assembly Language Syntax
3.3. Custom Instruction Word Format x
3.3.1. Selector and Extension Indexes 3.3.2. ALU Switch 3.3.3. User-defined Immediate
4. Designing with Intel® Quartus® Prime and Platform Designer x
4.1. Interface Signals 4.2. Custom Instruction Manager 4.3. Custom Instruction Subordinate
4.1. Interface Signals x
4.1.1. alu_result port 4.1.2. ctrl port
4.2. Custom Instruction Manager x
4.2.1. Hardware Interfaces Table 4.2.2. Software C-Macro Table
4.3. Custom Instruction Subordinate x
4.3.1. Writing the Custom Instruction HDL File 4.3.2. Opening the Component Editor 4.3.3. Specifying the Custom Instruction Component Type 4.3.4. Displaying the Custom Instruction Block Symbol 4.3.5. Adding the Custom Instruction HDL File 4.3.6. Configuring the Custom Instruction Parameter Type 4.3.7. Setting Up the Custom Instruction Interfaces 4.3.8. Saving and Adding the Custom Instruction 4.3.9. Generating and Compiling the Processor System
1. Nios® V Processor Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Designing with Intel® Quartus® Prime and Platform Designer
5. Document Revision History for AN 977: Nios® V Processor Custom Instruction

2.3. Extended Custom Instruction

Extended custom instruction is an extension to multicycle custom instructions. An extended custom instruction allows a single custom logic block to implement several different operations.

Extended custom instruction components implement multiple indexes, comprised of opcode, funct7, and funct3. These indexes are determined when the custom instruction hardware block is instantiated in the system using Platform Designer.

While the selector indexes (opcode and funct7[6:4]) are required to select the correct logic block, extended custom instructions decode extension indexes (funct7[3:0] and funct3[2:0]) to specify which operation in the logic block to perform. The extension index can be up to seven bits wide, allowing a single custom logic block to implement as many as 128 different operations. Paired with 32 logic blocks in a single Nios® V processor, this enables up to 4096 custom instructions per processor.

The following logic block shows an extended custom instruction with bit-swap, byte-swap, and half-word swap operations. This block performs all swap operations on data received at the data0 port. The instruction hardware uses the two-bits wide funct3 port to select the output from a multiplexer, determining which result is presented to the result port.
Figure 7. Extended Custom Instruction with Swap Operations
Note: The logic in the figure above is a simple example using a multiplexer on the output. You can implement function selection based on any extension indexes in any way that is appropriate for your application.

To implement an extended custom instruction, apply the ctrl port to your custom instruction logic. The total bit width of the funct7[3:0] and funct3[2:0] port is a function of the number of operations the custom logic block can perform.

Table 3.  32-bit Custom Instruction Word (ctrl)
32-bit Custom Instruction Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
funct7[6:0] rs2 rs1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rs1 funct3[2:0] rd opcode
Table 4.  Example of Selector and Extension Index Application
Selector Index Extension Index Supported Custom Instructions (per opcode)
opcode funct7[6:4] funct7[3:0] funct3[2:0]
custom-0 1 custom logic blocks Idle Idle 1 custom instructions
custom-1 8 custom logic blocks Idle Idle

8 custom instructions

(1 per logic block)
custom-2 8 custom logic blocks As extension index Idle

128 custom instructions

(16 per logic block)
custom-3 8 custom logic blocks As extension index As extension index

1024 custom instructions

(128 per logic block)
Total custom instruction in this processor 1161 custom instructions

Section Content
Extended Custom Instruction Timing

Level Two Title